BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260730T152640Z
LOCATION:
DTSTART;TZID=America/Los_Angeles:20260728T174100
DTEND;TZID=America/Los_Angeles:20260728T174100
UID:dac_DAC 2026_sess317_RESEARCH989@linklings.com
SUMMARY:TAMI-MPC: Trusted Acceleration of Minimal-Interaction MPC for Effi
 cient Nonlinear Inference
DESCRIPTION:Zhuoran Li and Hanieh TotonchiAsl (University of Arizona), Yif
 ei Cai (Iowa State University), Ebrahim Nouri (University of Arizona), and
  Danella Zhao (The University of Arizona)\n\nSecure multi-party computatio
 n (MPC) offers a practical foundation for privacy-preserving machine learn
 ing at the edge. However, current MPC systems rely heavily on communicatio
 n and computation-intensive primitives-such as secure comparison-for nonli
 near operations, which are often impractical on resource-constrained platf
 orms. To enable real-time secure inference, we introduce a highly efficien
 t, TEE-accelerated framework for secure comparison. Specifically, we reduc
 e communication cost by redesigning the core primitives-leaf comparison an
 d merge-so that each completes in a single round of interaction, reducing 
 the round complexity from log(n) to just 1 per operation. Furthermore, unl
 ike prior work that heavily relies on Oblivious Transfer (OT), a well-know
 n computational bottleneck, we leverage synchronized seeds inside the TEE 
 to eliminate OT for the vast majority of our designs, along with a correla
 ted-randomness reuse technique that keeps new designs computationally ligh
 tweight. To fully realize the potential, we design a specialized accelerat
 or that restructures the dataflow across stages to enable continuous, fine
 -grained streaming and high parallelism, reducing memory overhead. Our des
 ign achieves up to 4.86x speedup on ResNet-50 inference, compared with sta
 te-of-the-art CNN frameworks, and achieves up to 7.44x speedup on bert-bas
 e inference, compared with state-of-the-art LLM frameworks.\n\nTrack: EDA7
 -II. Physical Design and Verification, Design\n\nSession Chairs: Christian
  Pilato (Politecnico di Milano); Mohsen Imani (University of California, I
 rvine); Flavio Ponzina (San Diego State University); Amin Farshidi (Cadenc
 e Design Systems, Inc.); Yonggan Fu (Georgia Institute of Technology, NVID
 IA); Dimitrios Tsaras (Huawei, Hong Kong University of Science and Technol
 ogy (HKUST)); Anh Nguyen (Fujitsu Limited); Ruiyang Qin (Villanova Univers
 ity); Jiliang Zhang (Hunan University); Meng Li (Peking University); and R
 assul Bairamkulov (Advanced Micro Devices (AMD))\n\n
END:VEVENT
END:VCALENDAR
