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UID:dac_DAC 2026_sess317_RESEARCH907@linklings.com
SUMMARY:DRCGen: A Controllable DRC Violation Case Generator with Cross-PDK
  Transferability for Rule-Deck and Tool Validation
DESCRIPTION:Shunjie Chang, Yuxuan Dong, Haodong Lu, Youran Wu, Jianli Chen
 , Jun Yu, and Kun Wang (Fudan University)\n\nVLSI layout pattern generatio
 n plays a crucial role in design for manufacturability (DFM). Patterns tha
 t incorporate specific design rule checking (DRC) violations are valuable 
 for applications such as foundry design-rule deck development, EDA tool va
 lidation, and generating training data for AI-based DRC research. However,
  existing research primarily focuses on producing DRC-clean layouts by enf
 orcing rule compliance through constraints or filtering, while ignoring th
 e generation of controllable violations. To address this gap, we propose D
 RCGen, a controllable framework for generating DRC violation patterns with
  cross-PDK transferability. DRCGen is based on a diffusion model with cond
 itional control, generating structured control hints to encode spatial and
  semantic violation information for fine-tuning the model. The model can g
 enerate violation patterns of user-specified types within a target\nregion
  based on a natural-language prompt, while maintaining DRC-compliance outs
 ide the region. Additionally, we incorporate few-shot learning to facilita
 te rapid transfer across different PDKs. Experimental results show that, c
 ompared to state-of-the-art methods, our approach achieves a 2.27× increas
 e in topological diversity and a 1.02× increase in geometric diversity. Co
 mpared to Calibre LSG, we achieve 3.31× and 1.15× improvements in topologi
 cal and geometric diversity, respectively.\n\nTrack: EDA7-II. Physical Des
 ign and Verification, Design\n\nSession Chairs: Christian Pilato (Politecn
 ico di Milano); Mohsen Imani (University of California, Irvine); Flavio Po
 nzina (San Diego State University); Amin Farshidi (Cadence Design Systems,
  Inc.); Yonggan Fu (Georgia Institute of Technology, NVIDIA); Dimitrios Ts
 aras (Huawei, Hong Kong University of Science and Technology (HKUST)); Anh
  Nguyen (Fujitsu Limited); Ruiyang Qin (Villanova University); Jiliang Zha
 ng (Hunan University); Meng Li (Peking University); and Rassul Bairamkulov
  (Advanced Micro Devices (AMD))\n\n
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