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UID:dac_DAC 2026_sess317_RESEARCH885@linklings.com
SUMMARY:Chimera: A Unified FHE Accelerator with Enhanced Compatibility for
  TFHE
DESCRIPTION:Tenghui Hua (the Institute of Computing Technology, Chinese Ac
 ademy of Sciences at Beijing); Huawei Li (Institute of Computing Technolog
 y, Chinese Academy of Sciences); Jianan Mu (ICT, CAS); Jing Ye (State Key 
 Laboratory of Computer Architecture, Institute of Computing Technology, Ch
 inese Academy of Sciences); Liang Kong (Tsinghua University); and Mingzhe 
 Zhang (Institute of Computing Technology)\n\nFully homomorphic encryption 
 (FHE) allows direct computation on encrypted data and thus enables privacy
 -preserving computation in the cloud. Among FHE schemes, CKKS efficiently 
 supports arithmetic computation, while TFHE excels in logic operations. Re
 cent studies have attempted to develop unified FHE accelerators that suppo
 rt diverse computational tasks and leverage the complementary strengths of
  the two schemes. However, existing unified FHE accelerators are predomina
 ntly CKKS-centric. At the operator layer, TFHE is mapped onto CKKS-oriente
 d operators, causing significant performance degradation. Furthermore, the
  invocation to functional units and memory is entirely dominated by CKKS, 
 resulting in hardware underutilization for TFHE.\n\nIn this paper, we prop
 ose three coordinated co-optimizations to address these challenges. First,
  we unify the computation of Fast Fourier Transform (TFHE core operation) 
 and Number Theoretic Transform (CKKS core operation), and design a dual-mo
 de computational flow to efficiently support both computations. Second, we
  propose an aggressive strategy of bootstrapping key unrolling to maximize
  TFHE hardware utilization. Third, we design a hardware-oriented support f
 or FFT Shrinking KeySwitch to mitigate the performance bottleneck of TFHE 
 KeySwitch. Accordingly, we present Chimera, a unified accelerator that red
 esigns the functional units and memory organization for TFHE to efficientl
 y support these optimizations. Lastly, we develop an error, memory, and ba
 ndwidth-constrained auto-tuning framework that derives optimal TFHE config
 urations to maximize TFHE hardware utilization. Compared with the state-of
 -the-art unified FHE designs, Chimera achieves an average performance impr
 ovement by 14.84x across TFHE workloads, while maintaining comparable perf
 ormance on CKKS workloads, with only a 9.6% area increase.\n\nTrack: EDA7-
 II. Physical Design and Verification, Design\n\nSession Chairs: Christian 
 Pilato (Politecnico di Milano); Mohsen Imani (University of California, Ir
 vine); Flavio Ponzina (San Diego State University); Amin Farshidi (Cadence
  Design Systems, Inc.); Yonggan Fu (Georgia Institute of Technology, NVIDI
 A); Dimitrios Tsaras (Huawei, Hong Kong University of Science and Technolo
 gy (HKUST)); Anh Nguyen (Fujitsu Limited); Ruiyang Qin (Villanova Universi
 ty); Jiliang Zhang (Hunan University); Meng Li (Peking University); and Ra
 ssul Bairamkulov (Advanced Micro Devices (AMD))\n\n
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