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DTSTART;TZID=America/Los_Angeles:20260728T174000
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UID:dac_DAC 2026_sess317_RESEARCH754@linklings.com
SUMMARY:Delay-Constrained Area Optimisation Using SAT-Based Local Improvem
 ent
DESCRIPTION:Franz-Xaver Reichl (University of Freiburg) and Christoph Scho
 ll (University Freiburg)\n\nThis paper presents a new approach for minimis
 ing Boolean circuits subject to delay constraints.\nThe proposed approach 
 extends the efficient but purely area-based Boolean circuit minimiser eSLI
 M.\nThe eSLIM minimiser reduces circuits by iteratively computing optimal 
 replacements for small subcircuits on the fly.\nWe extend the SAT encoding
  used, for synthesising these replacements, to take account for delay.\nWh
 ile the additional constraints on delay restrict the set of possible candi
 dates for the replacement, we can still harness the flexibility of making 
 use of Boolean relations and multi-output circuits.\nWe implemented the pr
 oposed method as part of the industrial-strength tool ABC.\nSurprisingly, 
 in an experimental evaluation our implementation showed only a rather smal
 l deterioration in terms of area improvement, but substantial improvements
  in terms of delay compared to the purely area-based eSLIM approach on dif
 ferent benchmark sets.\n\nTrack: EDA7-II. Physical Design and Verification
 , Design\n\nSession Chairs: Christian Pilato (Politecnico di Milano); Mohs
 en Imani (University of California, Irvine); Flavio Ponzina (San Diego Sta
 te University); Amin Farshidi (Cadence Design Systems, Inc.); Yonggan Fu (
 Georgia Institute of Technology, NVIDIA); Dimitrios Tsaras (Huawei, Hong K
 ong University of Science and Technology (HKUST)); Anh Nguyen (Fujitsu Lim
 ited); Ruiyang Qin (Villanova University); Jiliang Zhang (Hunan University
 ); Meng Li (Peking University); and Rassul Bairamkulov (Advanced Micro Dev
 ices (AMD))\n\n
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