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DTSTART;TZID=America/Los_Angeles:20260728T175600
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UID:dac_DAC 2026_sess317_RESEARCH520@linklings.com
SUMMARY:Duplication-Aware Retiming and Cell Interface Redesign for Superco
 nductor Circuit Minimization
DESCRIPTION:Panagiotis Papanikolaou and Alex Vanasse (University of Wiscon
 sin-Madison), Haoran Jin (University of Michigan), and Georgios Tzimpragos
  and Jennifer Volk (University of Wisconsin-Madison)\n\nSuperconductor ele
 ctronics have increasingly shifted away from RSFQ and its variants toward 
 logic families that eliminate explicit gate-level clocking. While this tra
 nsition enables simpler circuits and more efficient architectures, it also
  introduces an implicit reliance on dual-rail codes, resulting in inherent
  gate duplication. This work presents a duplication-aware retiming methodo
 logy for Josephson junction (JJ) count minimization, co-optimizing registe
 r placement and polarity assignment. The approach applies beyond SFQ to an
 y monotonic circuit. We further identify cell interfaces—specifically, int
 erconnect drivers, receivers, and fanout (FO) elements—as dominant contrib
 utors to JJ count in each cell. A new amplifier design is introduced to re
 duce these costs, integrated within existing SFQ cells, experimentally ver
 ified, and characterized to form a new SFQ cell library. Our results demon
 strate a 63-71% JJ count reduction in single-cycle implementations and 41-
 66% reduction in multi-cycle implementations compared to the prior state-o
 f-the-art. The latter establishes a new Pareto frontier, achieving both sh
 orter critical paths and lower JJ counts than the best-to-date single-cycl
 e implementations.\n\nTrack: EDA7-II. Physical Design and Verification, De
 sign\n\nSession Chairs: Christian Pilato (Politecnico di Milano); Mohsen I
 mani (University of California, Irvine); Flavio Ponzina (San Diego State U
 niversity); Amin Farshidi (Cadence Design Systems, Inc.); Yonggan Fu (Geor
 gia Institute of Technology, NVIDIA); Dimitrios Tsaras (Huawei, Hong Kong 
 University of Science and Technology (HKUST)); Anh Nguyen (Fujitsu Limited
 ); Ruiyang Qin (Villanova University); Jiliang Zhang (Hunan University); M
 eng Li (Peking University); and Rassul Bairamkulov (Advanced Micro Devices
  (AMD))\n\n
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