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UID:dac_DAC 2026_sess317_RESEARCH407@linklings.com
SUMMARY:AMS Layout Automation Using Circuit-Level Analog Standard Cells an
 d Self-Biasing Techniques in Digital PnR Tools.
DESCRIPTION:Wonsik Oh and Luke Theogarajan (University of California, Sant
 a Barbara)\n\nThis work presents a silicon-verified analog–mixed-signal (A
 MS) layout-automation framework integrating a circuit-level analog standar
 d-cell (CLAS) library with self-biasing circuits in a digital place-and-ro
 ute (PnR) environment. Unlike transistor-level stem-cell approaches, the C
 LAS library standardizes matched circuit-level blocks, including self-bias
 ed amplifiers, current mirrors, and delay cells. Fabricated 180-nm and 65-
 nm CMOS chips validate fully automated, DRC/LVS-clean layouts for a curren
 t source, adaptive-bandwidth PLL, and probabilistic computer. All benchmar
 ks show strong pre-/post-layout and silicon correlation, with the PLL exhi
 biting 0.98–1.50 ps simulated and 4.1 ps measured jitter. The framework ac
 hieves ≥96 % area utilization, 14.4–69.5 % DCAP density, and <1 min–1 hr r
 untime, demonstrating scalable, silicon-consistent AMS automation.\n\nTrac
 k: EDA7-II. Physical Design and Verification, Design\n\nSession Chairs: Ch
 ristian Pilato (Politecnico di Milano); Mohsen Imani (University of Califo
 rnia, Irvine); Flavio Ponzina (San Diego State University); Amin Farshidi 
 (Cadence Design Systems, Inc.); Yonggan Fu (Georgia Institute of Technolog
 y, NVIDIA); Dimitrios Tsaras (Huawei, Hong Kong University of Science and 
 Technology (HKUST)); Anh Nguyen (Fujitsu Limited); Ruiyang Qin (Villanova 
 University); Jiliang Zhang (Hunan University); Meng Li (Peking University)
 ; and Rassul Bairamkulov (Advanced Micro Devices (AMD))\n\n
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