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DTSTART;TZID=America/Los_Angeles:20260728T173000
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UID:dac_DAC 2026_sess317_RESEARCH320@linklings.com
SUMMARY:SAAP: An Efficient Spatial-Aware Analytic Partitioning Algorithm o
 f VLSI Netlists for Parallel Routing
DESCRIPTION:CHEN LIU (Sun Yat-sen University), Hongxin Kong (Advanced Micr
 o Devices (AMD)), Lang Feng (Sun Yat-sen University), and Wenchao Qian and
  Wuxi Li (Advanced Micro Devices (AMD))\n\nAs VLSI designs grow in complex
 ity, partitioning is widely adopted to accelerate physical design through 
 parallel computing. However, traditional hypergraph partitioning methods o
 ften degrade in performance when applied to 2D layouts due to spatial cons
 traints. For routers with post-placement locations, a spatial-aware partit
 ioning method fully utilizing placement data is preferable. Existing works
  can only consider soft spatial constraints, leading to a scattered distri
 bution in one partition. We propose SAAP, an analytic partitioning algorit
 hm  enforcing hard spatial constraints while efficiently minimizing cut si
 zes. It includes analytic boundary modeling with regularity-guided simulat
 ed annealing and region embedding. Given placed netlists, it generates tim
 ing-friendly k-way spatially continuous partitions for parallel routing. E
 xperiments show that it can quickly provide several to dozens of times sma
 ller spatial cut sizes than previous state-of-the-art, with better spatial
  continuity.\n\nTrack: EDA7-II. Physical Design and Verification, Design\n
 \nSession Chairs: Christian Pilato (Politecnico di Milano); Mohsen Imani (
 University of California, Irvine); Flavio Ponzina (San Diego State Univers
 ity); Amin Farshidi (Cadence Design Systems, Inc.); Yonggan Fu (Georgia In
 stitute of Technology, NVIDIA); Dimitrios Tsaras (Huawei, Hong Kong Univer
 sity of Science and Technology (HKUST)); Anh Nguyen (Fujitsu Limited); Rui
 yang Qin (Villanova University); Jiliang Zhang (Hunan University); Meng Li
  (Peking University); and Rassul Bairamkulov (Advanced Micro Devices (AMD)
 )\n\n
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