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UID:dac_DAC 2026_sess317_RESEARCH3100@linklings.com
SUMMARY:Escaping Flatland: A Placement Flow for Enabling 3D FPGAs
DESCRIPTION:Cong "Callie" Hao (Georgia Institute of Technology); Andrew Ka
 hng and Bodhisatta Pramanik (University of California, San Diego); and Ism
 ael Youssef (Georgia Institute of Technology)\n\n3D field-programmable gat
 e arrays (FPGAs) promise higher performance through vertical integration. 
 However, existing placement tools, largely inherited from 2D frameworks, f
 ail to capture the unique delay characteristics and optimization dynamics 
 of 3D fabrics. We introduce a 3D FPGA placement flow that integrates parti
 tioning-based initialization, adaptive cost scheduling, refined delay esti
 mation, and a simulated annealing move set — all targeted at 3D FPGA archi
 tecture. Together, these enhancements improve timing estimates and the exp
 loration of layer assignments during placement. Compared to Verilog-To-Rou
 ting (VTR), our experiments show geometric-mean (max) critical-path delay 
 reductions of ∼3% (∼7%), ∼2% (∼4%), ∼3% (∼8%), and ∼6% (∼18%) for four 3D 
 architectures: 3D CB, 3D CB-O, 3D CB-I, and 3D SB, respectively. We also a
 chieve geometric-mean (max) routed wirelength reductions of ∼1% (∼3%), ∼2%
  (∼8%), < 1% (∼5%), and ∼5% (∼10%), respectively. Our work will be permiss
 ively open-sourced on GitHub.\n\nTrack: EDA7-II. Physical Design and Verif
 ication, Design\n\nSession Chairs: Christian Pilato (Politecnico di Milano
 ); Mohsen Imani (University of California, Irvine); Flavio Ponzina (San Di
 ego State University); Amin Farshidi (Cadence Design Systems, Inc.); Yongg
 an Fu (Georgia Institute of Technology, NVIDIA); Dimitrios Tsaras (Huawei,
  Hong Kong University of Science and Technology (HKUST)); Anh Nguyen (Fuji
 tsu Limited); Ruiyang Qin (Villanova University); Jiliang Zhang (Hunan Uni
 versity); Meng Li (Peking University); and Rassul Bairamkulov (Advanced Mi
 cro Devices (AMD))\n\n
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