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UID:dac_DAC 2026_sess317_RESEARCH2550@linklings.com
SUMMARY:MemFlow: Characterizing Memory Traffic Contention in Disaggregated
  Architectures
DESCRIPTION:Fujun He, Tuo Fang, Huaxiang Cai, Baolong Cui, Zhihe Zhang, Yi
 shan Yao, Xiabing Li, Linyi Du, Chuyue Ye, and Pingyi Huo (Huawei); Bin Ga
 o (National University of Singapore); Yiming Zhang (Shanghai Jiao Tong Uni
 versity); and Pengfei Zheng and Yunfei Du (Huawei)\n\nScale-up networks su
 pport memory semantics between pooled, disaggregated processor and memorie
 s; meanwhile, it triggers complex any-processor-to-any-memory accesses and
  creates intricate contention of micro-architectural components. Neverthel
 ess, existing simulators fail to adequately characterize the interference 
 due to oversimplified memory access paths. This paper presents the MemFlow
  simulator. MemFlow features a modular, fine-grained hardware abstraction 
 of disaggregated memory systems, provides a flow-centric simulation scheme
  to trace the complete memory access path from load-store queues through c
 ache hierarchies to memory controllers, evaluates micro-architectural cont
 ention with detail and fidelity, and enables automatic design space explor
 ation to mitigate contention-induce performance degradation.\n\nTrack: EDA
 7-II. Physical Design and Verification, Design\n\nSession Chairs: Christia
 n Pilato (Politecnico di Milano); Mohsen Imani (University of California, 
 Irvine); Flavio Ponzina (San Diego State University); Amin Farshidi (Caden
 ce Design Systems, Inc.); Yonggan Fu (Georgia Institute of Technology, NVI
 DIA); Dimitrios Tsaras (Huawei, Hong Kong University of Science and Techno
 logy (HKUST)); Anh Nguyen (Fujitsu Limited); Ruiyang Qin (Villanova Univer
 sity); Jiliang Zhang (Hunan University); Meng Li (Peking University); and 
 Rassul Bairamkulov (Advanced Micro Devices (AMD))\n\n
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