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UID:dac_DAC 2026_sess317_RESEARCH2416@linklings.com
SUMMARY:Area-Optimal and Routability-Driven Layout Synthesis for Multi-Row
  Complementary-FET Standard Cells
DESCRIPTION:Hao Wu, Keyu Peng, Fuxing Huang, Qiyuan Chen, and Zhengzhe Zhe
 ng (Southeast University); Jianli Chen (Fudan University); and Ziran Zhu (
 Southeast University)\n\nAs conventional FinFET architectures encounter se
 vere scaling limitations, Complementary-FET (CFET) technology with vertica
 lly stacked PMOS and NMOS transistors has emerged as a promising solution 
 for continued standard cell density scaling. However, aggressive area comp
 action in CFET standard cells drastically limits intra-cell routing resour
 ces, leading to routing congestion and design rule challenges. To mitigate
  this issue, multi-row CFET standard cell architectures have been introduc
 ed to improve intra-cell routability and alleviate block-level congestion.
  Nevertheless, these multi-row configurations introduce new placement-rout
 ing coupling and design rule complexities, making it challenging to achiev
 e compact, DRC-clean, and routable layouts. Therefore, this work proposes 
 an area-optimal and routability-driven layout synthesis framework for mult
 i-row CFET cells, which effectively addresses the challenges of area effic
 iency, constrained pin accessibility, and DRC compliance under multi-row C
 FET architectures. Therefore, this work proposes an area-optimal and routa
 bility-driven layout synthesis framework for multi-row CFET cells, which e
 ffectively addresses the challenges of area efficiency, constrained pin ac
 cessibility, and DRC compliance under multi-row CFET architectures. and (3
 ) a two-stage Satisfiability Modulo Theories (SMT)-based routing flow cons
 isting of a Multi-Commodity Flow (MCF)-based routability-guaranteed pin-ac
 cess selection and an Integer Linear Programming (ILP)-enhanced hierarchic
 al routing to ensure DRC/LVS closure. Compared with state-of-the-art multi
 -row CFET cell generators, experimental results show that our algorithm co
 nsistently achieves the optimal layout area, while delivering significant 
 improvements in solution quality and efficiency.\n\nTrack: EDA7-II. Physic
 al Design and Verification, Design\n\nSession Chairs: Christian Pilato (Po
 litecnico di Milano); Mohsen Imani (University of California, Irvine); Fla
 vio Ponzina (San Diego State University); Amin Farshidi (Cadence Design Sy
 stems, Inc.); Yonggan Fu (Georgia Institute of Technology, NVIDIA); Dimitr
 ios Tsaras (Huawei, Hong Kong University of Science and Technology (HKUST)
 ); Anh Nguyen (Fujitsu Limited); Ruiyang Qin (Villanova University); Jilia
 ng Zhang (Hunan University); Meng Li (Peking University); and Rassul Baira
 mkulov (Advanced Micro Devices (AMD))\n\n
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