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UID:dac_DAC 2026_sess317_RESEARCH2372@linklings.com
SUMMARY:TsetlinWiSARD: On-Chip Training of Weightless Neural Networks usin
 g Tsetlin Automata on FPGAs
DESCRIPTION:Shengyu Duan, Marcos Sartori, Rishad Shafik, and Alex Yakovlev
  (Newcastle University)\n\nThe growing need for environmental adaptability
 , privacy, and security in edge applications drives the search for alterna
 tives to deep learning that are both computationally efficient and hardwar
 e-friendly. WiSARD Weightless Neural Networks (WNNs) meet this need throug
 h simple table lookups, offering low latency and minimal computation. In t
 his work, we propose TsetlinWiSARD, an FPGA-based on-chip training archite
 cture for WiSARD WNNs that leverages Tsetlin Automata (TAs) to enable prob
 abilistic, feedback-driven learning. By mapping logical LUTs and TAs onto 
 physical LUTs on FPGAs, TsetlinWiSARD achieves state-of-the-art accuracy, 
 over 1000× faster training, and reduced resource use (22%), latency (93.3%
 ), and power (64.2%).\n\nTrack: EDA7-II. Physical Design and Verification,
  Design\n\nSession Chairs: Christian Pilato (Politecnico di Milano); Mohse
 n Imani (University of California, Irvine); Flavio Ponzina (San Diego Stat
 e University); Amin Farshidi (Cadence Design Systems, Inc.); Yonggan Fu (G
 eorgia Institute of Technology, NVIDIA); Dimitrios Tsaras (Huawei, Hong Ko
 ng University of Science and Technology (HKUST)); Anh Nguyen (Fujitsu Limi
 ted); Ruiyang Qin (Villanova University); Jiliang Zhang (Hunan University)
 ; Meng Li (Peking University); and Rassul Bairamkulov (Advanced Micro Devi
 ces (AMD))\n\n
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