BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260730T152640Z
LOCATION:
DTSTART;TZID=America/Los_Angeles:20260728T173400
DTEND;TZID=America/Los_Angeles:20260728T173400
UID:dac_DAC 2026_sess317_RESEARCH235@linklings.com
SUMMARY:Sandwich: Joint Configuration Search and Hot-Switching for Efficie
 nt CPU LLM Serving
DESCRIPTION:JUNTAO ZHAO, Jiuru Li, and Chuan Wu (The University of Hong Ko
 ng)\n\nCPUs are critical for LLM serving due to their availability, cost e
 fficiency, and edge applicability. However, efficient CPU serving is hinde
 red by conflicting prefill/decode resource demands under non-disaggregated
  deployment constraints—existing solutions fail to avoid cross-phase inter
 ference, ignore sub-NUMA hardware structures, and deliver suboptimal dynam
 ic-shape kernel performance.\nWe propose Sandwich, a full-stack CPU LLM se
 rving system with three core innovations addressing these challenges: (1) 
 seamless phase-wise plan switching to eliminate cross-phase interference; 
 (2) TopoTree, a tree-based hardware abstraction for automated substructure
 -aware (e.g., LLC slices) partial core allocation; (3) fast-start-then-fin
 etune dynamic-shape tensor program generation.\nEvaluated on five x86/ARM 
 CPU platforms, Sandwich achieves average 2.01× end-to-end speedup and up t
 o 3.40× latency reduction over SOTA systems. Its kernels match static comp
 iler performance with three orders of magnitude less tuning cost.\n\nTrack
 : EDA7-II. Physical Design and Verification, Design\n\nSession Chairs: Chr
 istian Pilato (Politecnico di Milano); Mohsen Imani (University of Califor
 nia, Irvine); Flavio Ponzina (San Diego State University); Amin Farshidi (
 Cadence Design Systems, Inc.); Yonggan Fu (Georgia Institute of Technology
 , NVIDIA); Dimitrios Tsaras (Huawei, Hong Kong University of Science and T
 echnology (HKUST)); Anh Nguyen (Fujitsu Limited); Ruiyang Qin (Villanova U
 niversity); Jiliang Zhang (Hunan University); Meng Li (Peking University);
  and Rassul Bairamkulov (Advanced Micro Devices (AMD))\n\n
END:VEVENT
END:VCALENDAR