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UID:dac_DAC 2026_sess317_RESEARCH2317@linklings.com
SUMMARY:UltraSketchLLM: Sub-1-Bit LLM Compression via Sketch and Hardware-
 Friendly Operators
DESCRIPTION:Sunan Zou, Xueting Sun, Ziyun Zhang, and Guojie Luo (Peking Un
 iversity)\n\nLarge language models (LLMs) require larger GPU memory space 
 these days, necessitating efficient and extreme weight compression methods
 . Existing compression methods are either theoretically limited by 1 bit p
 er weight or face severe performance degradation and inefficiency. To depl
 oy LLMs in resource-constrained scenarios, we introduce UltraSketchLLM, co
 mpressing LLMs with data sketch. It reduces peak GPU memory footprint with
  a high compression rate up to 0.5 bit per weight. Combined with hardware-
 friendly implementation, UltraSketchLLM keeps tolerable performance degrad
 ation and extremely low latency overhead with 14.9x speedup compared to na
 ive sketch solution.\n\nTrack: EDA7-II. Physical Design and Verification, 
 Design\n\nSession Chairs: Christian Pilato (Politecnico di Milano); Mohsen
  Imani (University of California, Irvine); Flavio Ponzina (San Diego State
  University); Amin Farshidi (Cadence Design Systems, Inc.); Yonggan Fu (Ge
 orgia Institute of Technology, NVIDIA); Dimitrios Tsaras (Huawei, Hong Kon
 g University of Science and Technology (HKUST)); Anh Nguyen (Fujitsu Limit
 ed); Ruiyang Qin (Villanova University); Jiliang Zhang (Hunan University);
  Meng Li (Peking University); and Rassul Bairamkulov (Advanced Micro Devic
 es (AMD))\n\n
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