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UID:dac_DAC 2026_sess317_RESEARCH2139@linklings.com
SUMMARY:Flip-FET-Based VLSI Design Framework with Congestion-Aware Dual-Si
 de Routing
DESCRIPTION:Sojung Park (UNIST); Junghyun Yoon (Ulsan National Institute o
 f Science and Technology (UNIST)); Jooyeon Jeong (University of California
 , Los Angeles); and Heechun Park (Ulsan National Institute of Science and 
 Technology (UNIST))\n\nThis paper presents a comprehensive Flip-FET-based 
 VLSI design framework that leverages both front-side and back-side metal l
 ayers for congestion-aware routing optimization. Starting from the placeme
 nt result, we formulate an integer linear programming (ILP) model to deter
 mine standard cells' pin assignments that minimize dual-side nets and alle
 viate regional congestion simultaneously. Routing is then performed with o
 ptimal nTSV insertion for dual-side nets using an RSMT construction approa
 ch. Experimental results demonstrate that the proposed framework achieves 
 78.8% reduction in maximum congestion and 68.6% reduction in DRVs over a c
 ommercial design tool.\n\nTrack: EDA7-II. Physical Design and Verification
 , Design\n\nSession Chairs: Christian Pilato (Politecnico di Milano); Mohs
 en Imani (University of California, Irvine); Flavio Ponzina (San Diego Sta
 te University); Amin Farshidi (Cadence Design Systems, Inc.); Yonggan Fu (
 Georgia Institute of Technology, NVIDIA); Dimitrios Tsaras (Huawei, Hong K
 ong University of Science and Technology (HKUST)); Anh Nguyen (Fujitsu Lim
 ited); Ruiyang Qin (Villanova University); Jiliang Zhang (Hunan University
 ); Meng Li (Peking University); and Rassul Bairamkulov (Advanced Micro Dev
 ices (AMD))\n\n
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