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UID:dac_DAC 2026_sess317_RESEARCH2037@linklings.com
SUMMARY:LRTA: Routability-Driven 3D-aware Track Assignment with Layer Reas
 signment
DESCRIPTION:Pengcheng Huang and Zepeng Li (Fuzhou University), Zhenkun Lin
  (Peking University), Guangyong Chen and Genggeng Liu (Fuzhou University),
  Wen-Hao Liu (NVIDIA), and Xing Huang (Northwestern Polytechnical Universi
 ty)\n\nAs the critical stage in chip design, routing comprises global rout
 ing and detailed routing, with track assignment (TA) serving as an interme
 diate step to bridge the two routing phases. However, existing methods con
 sider only 2D mismatches and overlook 3D coordination, resulting in degrad
 ed routing quality. This paper proposes LRTA, a routability-driven 3D-awar
 e track assignment framework with layer reassignment to coordinate the res
 ources across layers while preserving connectivity. In addition, a GPU-acc
 elerated TA scheme is proposed to construct candidates and dynamically ass
 ign tracks, enabling efficient concurrent evaluation.  Experimental result
 s demonstrate that, compared with existing works, the proposed LRTA achiev
 es significant improvements in routability estimation with shorter runtime
 .\n\nTrack: EDA7-II. Physical Design and Verification, Design\n\nSession C
 hairs: Christian Pilato (Politecnico di Milano); Mohsen Imani (University 
 of California, Irvine); Flavio Ponzina (San Diego State University); Amin 
 Farshidi (Cadence Design Systems, Inc.); Yonggan Fu (Georgia Institute of 
 Technology, NVIDIA); Dimitrios Tsaras (Huawei, Hong Kong University of Sci
 ence and Technology (HKUST)); Anh Nguyen (Fujitsu Limited); Ruiyang Qin (V
 illanova University); Jiliang Zhang (Hunan University); Meng Li (Peking Un
 iversity); and Rassul Bairamkulov (Advanced Micro Devices (AMD))\n\n
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