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DTSTART;TZID=America/Los_Angeles:20260728T174100
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UID:dac_DAC 2026_sess317_RESEARCH2024@linklings.com
SUMMARY:Rectilinear Soft Module Floorplanning via Differentiable Polygon S
 haping Model and Flow-based Legalization
DESCRIPTION:Fuxing Huang, Qiyuan Chen, Hao Wu, and Hao Gu (Southeast Unive
 rsity); Wenxing Zhu (Fuzhou University); and xinning liu and Ziran Zhu (So
 utheast University)\n\nFixed-outline floorplanning remains a critical chal
 lenge in VLSI physical design, particularly for modern System-on-Chips (So
 Cs) that employ rectilinear soft modules to maximize area utilization and 
 reduce wirelength. Existing methods adopt an incremental optimization stra
 tegy, introducing rectilinear shape considerations only after obtaining an
  initial rectangular solution. These approaches restrict module flexibilit
 y in early stages, limit the solution space, and degrade the final Quality
  of Results (QoR).We propose a unified floorplanning framework that, for t
 he first time, seamlessly integrates the optimization of rectilinear soft 
 module into both global floorplanning and legalization stages.To address t
 he computational challenges posed by rectilinear polygons, we introduce a 
 differentiable polygon shaping model that represents and dynamically optim
 izes module shapes using a structured set of continuous variables during g
 lobal floorplanning.We further design an augmented Lagrangian method to ef
 ficiently manage complex constraints with theoretical convergence guarante
 es, enhancing solution quality and stability. During legalization, we inge
 niously model the problem as a minimum-cost flow formulation, where the ob
 jective is to minimize the total displacement, thereby ensuring a legal an
 d high-quality final floorplan. Experimental results on GSRC and MCNC benc
 hmarks demonstrate that our method achieves better solution quality, reduc
 ing half-perimeter wirelength by an average of 4% and up to 14% compared w
 ith state-of-the-art floorplanners, while maintaining competitive runtime 
 performance.\n\nTrack: EDA7-II. Physical Design and Verification, Design\n
 \nSession Chairs: Christian Pilato (Politecnico di Milano); Mohsen Imani (
 University of California, Irvine); Flavio Ponzina (San Diego State Univers
 ity); Amin Farshidi (Cadence Design Systems, Inc.); Yonggan Fu (Georgia In
 stitute of Technology, NVIDIA); Dimitrios Tsaras (Huawei, Hong Kong Univer
 sity of Science and Technology (HKUST)); Anh Nguyen (Fujitsu Limited); Rui
 yang Qin (Villanova University); Jiliang Zhang (Hunan University); Meng Li
  (Peking University); and Rassul Bairamkulov (Advanced Micro Devices (AMD)
 )\n\n
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