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UID:dac_DAC 2026_sess317_RESEARCH2007@linklings.com
SUMMARY:TransSyn: Scalable, Area-Oriented Transistor Network Synthesis via
  Cut-Based Mapper with SAT-Based Refinement
DESCRIPTION:Jiun-Cheng Tsai, Wei-Min Hsu, Hsuan-Ming Huang, Jen-Hang Yang,
  and Heng-Liang Huang (MediaTek) and Yen-Ju Su and Hung-Pin (Charles) Wen 
 (National Yang Ming Chiao Tung University)\n\nSAT-based transistor network
  synthesis delivers optimal, minimum-transistor designs but faces exponent
 ial complexity, making it impractical for large circuits. This paper intro
 duces TransSyn, a scalable transistor network synthesizer that brings the 
 benefits of SAT-based synthesis to the macro-cell scale through a novel tw
 o-stage framework. First, a cut-based global synthesis stage reformulates 
 the task as a cut-based mapping problem, rapidly decomposing the design in
 to smaller, manageable sub-problems. This ensures scalability and produces
  a high-quality network in seconds. Then, a SAT-based detailed synthesis s
 tage refines this network by systematically identifying and re-optimizing 
 merged subcircuits across cut boundaries using a SAT-based approach, recap
 turing lost optimization opportunities. Experiments demonstrate that Trans
 Syn significantly outperforms previous methods, achieving 11.2% and 10% re
 ductions in transistor count compared to graph-based and hybrid-based appr
 oaches, respectively. Furthermore, when integrated with a transistor-level
  placer, TransSyn breaks the library and cell boundaries, yielding up to a
  48.8% area reduction compared to conventional cell-based designs. TransSy
 n demonstrates its capability for scalable, high-quality transistor-networ
 k synthesis, successfully bridging the gap between the optimality of SAT-b
 ased synthesis and the practical demands of large-scale cell design.\n\nTr
 ack: EDA7-II. Physical Design and Verification, Design\n\nSession Chairs: 
 Christian Pilato (Politecnico di Milano); Mohsen Imani (University of Cali
 fornia, Irvine); Flavio Ponzina (San Diego State University); Amin Farshid
 i (Cadence Design Systems, Inc.); Yonggan Fu (Georgia Institute of Technol
 ogy, NVIDIA); Dimitrios Tsaras (Huawei, Hong Kong University of Science an
 d Technology (HKUST)); Anh Nguyen (Fujitsu Limited); Ruiyang Qin (Villanov
 a University); Jiliang Zhang (Hunan University); Meng Li (Peking Universit
 y); and Rassul Bairamkulov (Advanced Micro Devices (AMD))\n\n
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