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UID:dac_DAC 2026_sess317_RESEARCH1942@linklings.com
SUMMARY:PD-Swap: Prefill–Decode Logic Swapping for End-to-End LLM Inferenc
 e on Edge FPGAs via Dynamic Partial Reconfiguration
DESCRIPTION:Yifan Zhang, Zhiheng Chen, Ye Qiao, Zhenyu Tang, and Sitao Hua
 ng (University of California, Irvine)\n\nAggressively quantized large lang
 uage models (LLMs), such as BitNet-style 1.58-bit Transformers with ternar
 y weights, make it feasible to deploy generative AI on low-power edge FPGA
 s. As prompts grow to tens of thousands of tokens, edge hardware performan
 ce drops sharply with sequence length due to quadratic prefill cost and ra
 pidly increasing KV-cache bandwidth demands, making context length a first
 -order systems concern. Recent work with table-lookup-based ternary matrix
  multiplication on edge FPGAs exposes a fundamental prefill--decode asymme
 try: prefill is compute-bound and dominated by dense matrix--matrix operat
 ions, whereas decoding is memory-bandwidth-bound and dominated by KV-cache
  traffic. A static accelerator must provision resources and a single dataf
 low for both regimes, leading to duplicated attention logic, underutilized
  fabric, and tight LUT/URAM limits that cap model size and usable context.
  We propose a prefill--decode disaggregated LLM accelerator that uses Dyna
 mic Patial Reconfiguration (DPR) to time-multiplex the attention module on
  edge FPGAs. The core table-lookup ternary matrix multiplication and weigh
 t-buffering engines remain static, while the attention subsystem is a reco
 nfigurable partition with two phase-specialized dataflows: a compute-heavy
 , token-parallel prefill engine and a bandwidth-optimized, KV-cache-centri
 c decoding engine. A roofline-inspired model and design space exploration 
 jointly optimize reconfigurable-region size, parallelism under reconfigura
 tion and routability constraints, and partial reconfiguration is overlappe
 d with ongoing computation. Our design achieves state-of-the-art performan
 ce, with up to 27~tokens/s decoding throughput. Compared with the prior st
 atic design, PD-Swap achieves a 1.3x--2.1x speedup, with larger gains at l
 onger context lengths.\n\nTrack: EDA7-II. Physical Design and Verification
 , Design\n\nSession Chairs: Christian Pilato (Politecnico di Milano); Mohs
 en Imani (University of California, Irvine); Flavio Ponzina (San Diego Sta
 te University); Amin Farshidi (Cadence Design Systems, Inc.); Yonggan Fu (
 Georgia Institute of Technology, NVIDIA); Dimitrios Tsaras (Huawei, Hong K
 ong University of Science and Technology (HKUST)); Anh Nguyen (Fujitsu Lim
 ited); Ruiyang Qin (Villanova University); Jiliang Zhang (Hunan University
 ); Meng Li (Peking University); and Rassul Bairamkulov (Advanced Micro Dev
 ices (AMD))\n\n
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