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UID:dac_DAC 2026_sess317_RESEARCH1885@linklings.com
SUMMARY:PEACE: Algorithm–Hardware Co-Design for PE-Granular Energy-Aware C
 ompressed GEMM Acceleration
DESCRIPTION:yueting Li (Hangzhou International Innovation Institute, Beiha
 ng University); Terry Ye (The Chinese University of Hong Kong); He Xiao, Z
 heng Liu, and Ngai Wong (University of Hong Kong); and Weisheng Zhao (Beih
 ang University)\n\nGeneral matrix–matrix multiplication (GEMM) remains the
  dominant compute kernel in transformer-based large language model (LLM) i
 nference.\nHowever, large-scale matrices exhibiting irregular sparsity fun
 damentally limit throughput and energy efficiency in existing systems.\nTo
  address these challenges, we propose PEACE, an energy-aware matrix compre
 ssion framework for accelerating GEMM operations at the processing element
  (PE)-array granularity.\nPEACE comprises a novel matrix compression algor
 ithm, PEACE-Alg, which reorganizes large-scale matrices into hardware-frie
 ndly compressed formats by exploiting the column-wise energy distribution.
 \nTo support PEACE-Alg, we design a hardware microarchitecture, PEACE-Hw, 
 that integrates RISC-V ISA extensions with a table-metadata fetcher and a 
 metadata-driven operand loader to feed a reconfigurable systolic PE array,
  and a dedicated partial-sum adder for efficiently merging intermediate re
 sults.\nExperimental results show that PEACE occupies 2.705 mm^2 in a 14 n
 m ASIC and delivers a peak INT8 throughput of 88 GOPS/W.  \nPEACE achieves
  1.60×-1.67× speedup over a RISC-V core baseline across 14 transformer-bas
 ed LLMs.\nCompared with state-of-the-art designs, PEACE  provides 4.4× hig
 her PE density, 1.79× average speedup and 2.53× energy efficiency.\n\nTrac
 k: EDA7-II. Physical Design and Verification, Design\n\nSession Chairs: Ch
 ristian Pilato (Politecnico di Milano); Mohsen Imani (University of Califo
 rnia, Irvine); Flavio Ponzina (San Diego State University); Amin Farshidi 
 (Cadence Design Systems, Inc.); Yonggan Fu (Georgia Institute of Technolog
 y, NVIDIA); Dimitrios Tsaras (Huawei, Hong Kong University of Science and 
 Technology (HKUST)); Anh Nguyen (Fujitsu Limited); Ruiyang Qin (Villanova 
 University); Jiliang Zhang (Hunan University); Meng Li (Peking University)
 ; and Rassul Bairamkulov (Advanced Micro Devices (AMD))\n\n
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