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UID:dac_DAC 2026_sess317_RESEARCH1813@linklings.com
SUMMARY:RL4HDL: Code Diversity Guided FPGA Logic Synthesis Compiler Testin
 g Via Reinforcement Learning
DESCRIPTION:Zhihao Xu, Hui Zeng, Hui Li, Qian Ma, Furui Zhan, and Shikai G
 uo (Dalian Maritime University)\n\nLogic synthesis compilers play an indis
 pensable role in FPGA design, translating register-transfer-level (RTL) de
 scriptions into gate-level netlists. Defects in these compilers may compro
 mise the security of the final hardware implementations. Existing testing 
 methods often produce redundant test cases, which limits their ability to 
 effectively explore compiler defects. To address this problem, we propose 
 RL4HDL, a new method that uses reinforcement learning to guide logic synth
 esis compiler testing. Comprehensive experiments conducted over a three-mo
 nth period demonstrate the practical effectiveness of our approach: we dis
 covered 20 unique defects, including 12 previously unreported ones, all of
  which have been confirmed by the official developers.\n\nTrack: EDA7-II. 
 Physical Design and Verification, Design\n\nSession Chairs: Christian Pila
 to (Politecnico di Milano); Mohsen Imani (University of California, Irvine
 ); Flavio Ponzina (San Diego State University); Amin Farshidi (Cadence Des
 ign Systems, Inc.); Yonggan Fu (Georgia Institute of Technology, NVIDIA); 
 Dimitrios Tsaras (Huawei, Hong Kong University of Science and Technology (
 HKUST)); Anh Nguyen (Fujitsu Limited); Ruiyang Qin (Villanova University);
  Jiliang Zhang (Hunan University); Meng Li (Peking University); and Rassul
  Bairamkulov (Advanced Micro Devices (AMD))\n\n
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