BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260730T152640Z
LOCATION:
DTSTART;TZID=America/Los_Angeles:20260728T175500
DTEND;TZID=America/Los_Angeles:20260728T175500
UID:dac_DAC 2026_sess317_RESEARCH1534@linklings.com
SUMMARY:DRΛMA: Detailed Routing by a Versatile Maze Routing Algorithm
DESCRIPTION:Jinwei Liu (Hong Kong Baptist University) and Xingyu Cui, Lian
 g Xiao, Bangqi Fu, and Evangeline Young (The Chinese University of Hong Ko
 ng)\n\nDetailed routing, despite its long history of study, is considered 
 one\nof the most challenging problems in Electronic Design Automation,\ndu
 e to complex design rules and enormous scale. In this work, we\npropose a 
 versatile maze routing algorithm to deal with the various\nchallenges in d
 etailed routing. By introducing hybrid grid graph, our\nmaze routing algor
 ithm can create both on-track and off-track wires\nduring path search. By 
 adopting a scalable track-based resource\nmodel and techniques like adapti
 ve grid graph sparsification, it can\nhandle both large guide-based and sm
 all region-based grid graphs.\nMoreover, we also propose a simple and effe
 ctive rip-up and reroute\nstrategy. As a result, we achieve design rule vi
 olation-free on most\ndesigns (9/10) in the ISPD 2018 detailed routing ben
 chmarks, with\n2.5% better score, 4.6% fewer vias, and 14.7% shorter runti
 me on\naverage, and significantly lower non-preferred usage, compared\nwit
 h the state-of-the-art approaches.\n\nTrack: EDA7-II. Physical Design and 
 Verification, Design\n\nSession Chairs: Christian Pilato (Politecnico di M
 ilano); Mohsen Imani (University of California, Irvine); Flavio Ponzina (S
 an Diego State University); Amin Farshidi (Cadence Design Systems, Inc.); 
 Yonggan Fu (Georgia Institute of Technology, NVIDIA); Dimitrios Tsaras (Hu
 awei, Hong Kong University of Science and Technology (HKUST)); Anh Nguyen 
 (Fujitsu Limited); Ruiyang Qin (Villanova University); Jiliang Zhang (Huna
 n University); Meng Li (Peking University); and Rassul Bairamkulov (Advanc
 ed Micro Devices (AMD))\n\n
END:VEVENT
END:VCALENDAR
