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UID:dac_DAC 2026_sess317_RESEARCH1434@linklings.com
SUMMARY:G-Matcher: GPU-Accelerated Multi-Level, Multi-Stage Framework for 
 Large-Scale Layout Pattern Matching
DESCRIPTION:Nan Wang, Hanbin Dong, and Chengxuan Lv (ShanghaiTech Universi
 ty); Jiaqi Liu (Shanghai Optoelectronics Science and Technology Innovation
  Center); and Tao Wu, Jingyi Yu, and Hao Geng (ShanghaiTech University)\n\
 nPattern matching has become one of the most predominant industrial soluti
 ons in IC design-to-manufacturing flow, with broad applications in layout 
 verification, hotspot detection and Optical Proximity Correction (OPC). Ho
 wever, conventional CPU-based approaches, which rely on rule-based extract
 ion, suffer from excessive false matches and high runtime overhead. These 
 inefficiencies create bottlenecks in both verification and manufacturing w
 orkflows at advanced nodes. To address these limitations, we introduce the
  first fully GPU-accelerated pattern matching framework G-Matcher, with a 
 novel multi-stage, multi-level architecture. Our GPU-oriented development 
 exploits massive parallelism to process ultra large scale layout data. The
  multi-stage pipeline filters false matches, while the multi-level paradig
 m utilizes specialized pattern and layout representations to accelerate th
 e search. On industrial datasets, our framework demonstrates a 407× speedu
 p over the 64-thread commercial tool Calibre. On public benchmarks, it ach
 ieves 7.1× speedup over a state-of-the-art CPU implementation. Importantly
 , G-Matcher maintains 100% matching accuracy with zero false matches acros
 s all evaluations.\n\nTrack: EDA7-II. Physical Design and Verification, De
 sign\n\nSession Chairs: Christian Pilato (Politecnico di Milano); Mohsen I
 mani (University of California, Irvine); Flavio Ponzina (San Diego State U
 niversity); Amin Farshidi (Cadence Design Systems, Inc.); Yonggan Fu (Geor
 gia Institute of Technology, NVIDIA); Dimitrios Tsaras (Huawei, Hong Kong 
 University of Science and Technology (HKUST)); Anh Nguyen (Fujitsu Limited
 ); Ruiyang Qin (Villanova University); Jiliang Zhang (Hunan University); M
 eng Li (Peking University); and Rassul Bairamkulov (Advanced Micro Devices
  (AMD))\n\n
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