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UID:dac_DAC 2026_sess317_RESEARCH130@linklings.com
SUMMARY:C2C-Explorer: An Exploration Framework for Chip-to-Chip Interconne
 ct Architectures in LLM Cloud Computing Systems
DESCRIPTION:Jiayi Li (Peking University); Di Wu and Qingxu Li (Alibaba); H
 ongxiao Zhao, Jiaqi Yang, and Anjunyi Fan (Peking University); Wenbin Zhan
 g, Boqiang Wu, Shuting Liu, Shifeng Fang, Jianbo Dong, and Dimin Niu (Alib
 aba); and Bonan Yan (Peking University)\n\nThe scaling-up of large languag
 e models (LLMs) necessitates computing systems to have multi-processor-chi
 p architectures, elevating the importance of chip-to-chip (C2C) communicat
 ion. However, designing efficient C2C hardware architectures for LLM workl
 oads faces three key challenges: generating realistic LLM-specific C2C tra
 ffic, accurately simulating hardware-level communication at scale, and eff
 iciently exploring the exponentially large C2C design space. We propose C2
 C-Explorer, an adaptive Bayesian DSE framework that integrates a LLM-workl
 oad-driven traffic generator, a scalable interconnect simulator (switch/fu
 ll-mesh, up to 512 chips), and a metric-guided evaluator into a workload-t
 o-hardware optimization pipeline, enabling systematic C2C architectural co
 -design under realistic LLM workloads. Validated against FPGA-based C2C pr
 ototypes, the C2C simulator achieves 2.46–8.23% end-to-end timing error ac
 ross diverse traffic patterns. Its hybrid cycle & event model further acce
 lerates large-scale simulation by up to 7.8× over a pure cycle-accurate ba
 seline.  Applied to a 32-XPU DeepSeek-R1-671B inference workload, C2C-Expl
 orer identifies configurations that improve goodput by 44.1% and reduce me
 mory by 98.4%. C2C-Explorer is open-source and available at https://anonym
 ous.4open.science/r/C2C-Explorer.\n\nTrack: EDA7-II. Physical Design and V
 erification, Design\n\nSession Chairs: Christian Pilato (Politecnico di Mi
 lano); Mohsen Imani (University of California, Irvine); Flavio Ponzina (Sa
 n Diego State University); Amin Farshidi (Cadence Design Systems, Inc.); Y
 onggan Fu (Georgia Institute of Technology, NVIDIA); Dimitrios Tsaras (Hua
 wei, Hong Kong University of Science and Technology (HKUST)); Anh Nguyen (
 Fujitsu Limited); Ruiyang Qin (Villanova University); Jiliang Zhang (Hunan
  University); Meng Li (Peking University); and Rassul Bairamkulov (Advance
 d Micro Devices (AMD))\n\n
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