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UID:dac_DAC 2026_sess317_RESEARCH1268@linklings.com
SUMMARY:Bident: Optical Logic Synthesis via Optimal Configuration of Binar
 y-Combiner Trees
DESCRIPTION:Jun-Wei Liang, Iris Hui-Ru Jiang, and Kai-Hsiang Chiu (Nationa
 l Taiwan University)\n\nDespite decades of success, CMOS technology is inc
 reasingly constrained by power dissipation and propagation delay, thus mot
 ivating the exploration of photonic integrated circuits as an alternative 
 for high-speed, energy-efficient computing. However, existing optical logi
 c synthesis frameworks rely on an oversimplified efficiency factor model t
 hat fails to accurately capture physical attenuation and the hierarchical 
 nature of signal degradation. This work presents Bident, a comprehensive o
 ptical logic synthesis framework that provides a physically accurate loss 
 model and achieves optimal combiner configuration. We introduce the binary
  aggregate model, which explicitly reflects the binary-tree topology and i
 nput ordering in multi-input combiners. Based on this model, the Huffman t
 ree optimization guarantees optimal Y-branch combiner configuration withou
 t requiring additional hardware resources. Meanwhile, a greedy algorithm o
 ptimally employs directional couplers at the leaf layer of a binarycombine
 r tree to achieve harmonic-mean efficiency at minimal hardware cost. Exper
 imental results demonstrate that Bident achieves superior signal-attenuati
 on reduction and lower switch cost than state-of-the-art methods, using bo
 th the conventional efficiency factor model and our binary aggregate model
 . A schematic-level optical circuit simulation further validates the feasi
 bility and effectiveness of our binary-combiner configurations.\n\nTrack: 
 EDA7-II. Physical Design and Verification, Design\n\nSession Chairs: Chris
 tian Pilato (Politecnico di Milano); Mohsen Imani (University of Californi
 a, Irvine); Flavio Ponzina (San Diego State University); Amin Farshidi (Ca
 dence Design Systems, Inc.); Yonggan Fu (Georgia Institute of Technology, 
 NVIDIA); Dimitrios Tsaras (Huawei, Hong Kong University of Science and Tec
 hnology (HKUST)); Anh Nguyen (Fujitsu Limited); Ruiyang Qin (Villanova Uni
 versity); Jiliang Zhang (Hunan University); Meng Li (Peking University); a
 nd Rassul Bairamkulov (Advanced Micro Devices (AMD))\n\n
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