BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260730T152640Z
LOCATION:
DTSTART;TZID=America/Los_Angeles:20260728T174300
DTEND;TZID=America/Los_Angeles:20260728T174300
UID:dac_DAC 2026_sess317_RESEARCH1211@linklings.com
SUMMARY:DCTS: Differentiable Clock Tree Synthesis Based on Probabilistic G
 raphical Model
DESCRIPTION:han zhang, Junming Jiao, Zhi Li, Qixun Tian, and Peng Cao (Sou
 theast University)\n\nClock Tree Synthesis (CTS) constitutes a complex, di
 screte, and combinatorial multi-objective optimization (MOO) problem, whic
 h is typically fragmented into sequential steps, including clustering, top
 ology generation, and buffering in traditional flows, leading to suboptima
 l results due to local optima. Despite significant potential in MOO, diffe
 rentiable methods are inherently limited to represent dynamic topological 
 adjustments during CTS. To solve this, We propose an end-to-end differenti
 able CTS framework, DCTS, based on  Probabilistic Graphical Model (PGM) to
  re-parameterize the discrete topological search into a continuous gradien
 t-based problem, enabling co-optimization of clock tree topology and buffe
 r sizing within a global design space. The proposed DCTS was evaluated on 
 ISCAS'89 and OpenCores benchmark circuits under the ASAP7 technology node.
  Experimental results show that it achieves competitive power, performance
 , and area (PPA) metrics against a leading commercial tool, along with a 2
 .78$\times$ speedup on large-scale circuits. Furthermore, when compared to
  state-of-the-art academic solutions, DCTS guarantees minimum improvements
  of 20\% in delay, 17\% in skew, 1\% in power, and 17\% in area, while als
 o achieving a minimum speedup of 1.98$\times$ on large-scale designs.\n\nT
 rack: EDA7-II. Physical Design and Verification, Design\n\nSession Chairs:
  Christian Pilato (Politecnico di Milano); Mohsen Imani (University of Cal
 ifornia, Irvine); Flavio Ponzina (San Diego State University); Amin Farshi
 di (Cadence Design Systems, Inc.); Yonggan Fu (Georgia Institute of Techno
 logy, NVIDIA); Dimitrios Tsaras (Huawei, Hong Kong University of Science a
 nd Technology (HKUST)); Anh Nguyen (Fujitsu Limited); Ruiyang Qin (Villano
 va University); Jiliang Zhang (Hunan University); Meng Li (Peking Universi
 ty); and Rassul Bairamkulov (Advanced Micro Devices (AMD))\n\n
END:VEVENT
END:VCALENDAR