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UID:dac_DAC 2026_sess317_RESEARCH1183@linklings.com
SUMMARY:Dynamic-Cost Area Recovery for Fracturable LUT-Based FPGAs
DESCRIPTION:Xianfeng Cao, Jiangnan Li, and Lingli Wang (Fudan University)\
 n\nFracturable LUTs (FLUTs) creates variable logic consumption for LUT imp
 lementations since two LUTs can be merged to one FLUT under certain constr
 aints. Traditional technology mapping algorithms fail to exploit this feat
 ure due to their static-cost area models. To bridge this gap, we introduce
  merging probability, a quantitative, mapping-stage metric that predicts t
 he likelihood of LUT merging during the subsequent packing phase. Based on
  this, we present a dynamic-cost LUT area model, enabling area recovery be
 tter suited for FLUTs. Experimental results on EPFL benchmarks demonstrate
  that our method reduces the usage of FLUTs by at most of 10.3% on mainstr
 eam commercial FPGAs, compared to the state-of-the-art technology mapping 
 algorithm, without any performance degradation.\n\nTrack: EDA7-II. Physica
 l Design and Verification, Design\n\nSession Chairs: Christian Pilato (Pol
 itecnico di Milano); Mohsen Imani (University of California, Irvine); Flav
 io Ponzina (San Diego State University); Amin Farshidi (Cadence Design Sys
 tems, Inc.); Yonggan Fu (Georgia Institute of Technology, NVIDIA); Dimitri
 os Tsaras (Huawei, Hong Kong University of Science and Technology (HKUST))
 ; Anh Nguyen (Fujitsu Limited); Ruiyang Qin (Villanova University); Jilian
 g Zhang (Hunan University); Meng Li (Peking University); and Rassul Bairam
 kulov (Advanced Micro Devices (AMD))\n\n
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