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UID:dac_DAC 2026_sess315_RESEARCH401@linklings.com
SUMMARY:PAGE: Processing-Using-DRAM Architecture-Circuits Co-Optimization 
 for Efficient Acceleration of General Matrix-Vector Multiplication
DESCRIPTION:Yifan He and Hyung Joon Byun (Cornell University); Jimin Lee (
 SK hynix); Do-Yoon Lim (Cornell University); Houxiang Ji, Jungmin Choi, an
 d Hoshik Kim (SK hynix); and Jae-sun Seo (Cornell University)\n\nAs large 
 language models (LLMs) continue to scale in size and complexity, DRAM acce
 ss has become a performance bottleneck, especially during the memory-bound
  decoding phase dominated by general matrix-vector multiplication (GEMV) o
 perations. Recent work has explored near-/in-memory computing to address b
 andwidth limitations. Among these, Processing-Using-DRAM (PUD) offers a un
 ique advantage as it performs logic operations entirely within DRAM periph
 erals with minimal circuit changes, enabling deployment on commercial off-
 the-shelf (COTS) DRAM. While prior work reported multi-input logic operati
 ons, its potential to accelerate GEMV operations in LLMs remains underexpl
 ored due to the limited compute capability of DRAM sense amplifiers (SAs).
 \nTo overcome this challenge, we propose PAGE, a PUD architecture that acc
 elerates GEMV through four key optimizations: (1) mat-level parallelism th
 at exploits row-level parallelism by activating SAs across multiple mats; 
 (2) inversion-enabled SA supporting NOT operations within a mat; (3) AP-ba
 sed row copy mechanism that performs simultaneous source–destination activ
 ation with only control-signal changes; and (4) adaptive adder-tree accumu
 lation that reduces accumulation cycles. We demonstrate the baseline PUD a
 rchitecture on a COTS DRAM–FPGA platform to verify the functionality and t
 iming of PUD operations, implement the modified circuits in TSMC 16nm for 
 circuit-level evaluation, and build a in-house simulator for system-level 
 throughput and energy analysis. Overall, PAGE achieves up to 14× and 3.1× 
 end-to-end throughput and energy improvement for GEMV workloads over the S
 oTA PUD designs, demonstrating its feasibility for accelerating memory-bou
 nd LLM workloads with PUD.\n\nTopics: Quantum\n\nTrack: DES6. Quantum Comp
 uting, Systems\n\nSession Chairs: Hokeun Kim (Arizona State University); B
 aekGyu Kim (Daegu Gyeongbuk Institute of Science and Technology); Xiang Ch
 en (Peking University); Sangyeob Kim (Yonsei University); Robert M. Radway
  (University of Pennsylvania); Prashanth Mohan (University of Pittsburgh);
  Xiaoxuan Yang (University of Virginia, Stanford University); Ramtin Zand 
 (University of South Carolina); Hadi Kamali (University of Central Florida
 ); Jiafeng Xie (Villanova University); Prabuddha Chakraborty (University o
 f Maine); Junichiro Kadomoto (University of Tokyo); and Yosuke Ueno (RIKEN
 )\n\n
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