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UID:dac_DAC 2026_sess315_RESEARCH282@linklings.com
SUMMARY:HiBand: A Hierarchical Bandwidth-Aware HB-DRAM Accelerator with Ar
 ray-Level Co-Execution and Reconfigurable NoC for LLM Inference
DESCRIPTION:Huanyu Wang, Yang Wang, Yutong Su, Jiaxin Yang, Yang Hu, and S
 houyi Yin (Tsinghua University)\n\nHybrid-bonding 3D DRAM (HB-DRAM) delive
 rs massive in-situ bandwidth but shifts LLM accelerator bottlenecks from o
 ff-chip memory to the Network-on-Chip, where decentralized bank-local band
 width must be coordinated across arrays. We present HiBand, a bandwidth-aw
 are HB-DRAM accelerator that co-designs array-level execution with a four-
 mode reconfigurable NoC. HiBand combines grouped tensor parallelism and cr
 oss-head array-level co-execution to confine most traffic to short-range l
 inks while overlapping bandwidth-bound attention with compute-bound feed-f
 orward layers. On LLM models mapped to a 32-array HB-DRAM accelerator, HiB
 and achieves up to 4.28× speedup over an HBM3 GPU-style accelerator and 1.
 67× speedup over a state-of-the-art HB-DRAM–based NMP design.\n\nTopics: Q
 uantum\n\nTrack: DES6. Quantum Computing, Systems\n\nSession Chairs: Hokeu
 n Kim (Arizona State University); BaekGyu Kim (Daegu Gyeongbuk Institute o
 f Science and Technology); Xiang Chen (Peking University); Sangyeob Kim (Y
 onsei University); Robert M. Radway (University of Pennsylvania); Prashant
 h Mohan (University of Pittsburgh); Xiaoxuan Yang (University of Virginia,
  Stanford University); Ramtin Zand (University of South Carolina); Hadi Ka
 mali (University of Central Florida); Jiafeng Xie (Villanova University); 
 Prabuddha Chakraborty (University of Maine); Junichiro Kadomoto (Universit
 y of Tokyo); and Yosuke Ueno (RIKEN)\n\n
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