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UID:dac_DAC 2026_sess315_RESEARCH270@linklings.com
SUMMARY:3D-ReSAC: A Near-3D-Stacked-DRAM Processor with Area-Efficient Seq
 uential Refresh-Skip and High-Link-Utilization ArrowMesh Communication for
  Fast Low-batch LLM Inference
DESCRIPTION:Wenbin Jia and Haocheng Li (Tsinghua University), Xiang Li (Ts
 inghua), and Xinyuan Lin and Yongpan Liu (Tsinghua University)\n\nLow-batc
 h LLM inference on edge hardware places stringent demands on both memory b
 andwidth and computational capacity. While 3D-stacked DRAM accelerators of
 fer a promising solution, they introduce two critical overheads that are f
 requently under-optimized: DRAM refresh and collective communication.\nTo 
 mitigate these issues, we propose 3D-ReSAC, a near-memory processor based 
 on 3D-stacked DRAM, equipped with an area-efficient sequential refresh-ski
 p method and high-link-utilization ArrowMesh communication.\nOur evaluatio
 ns show that 3D-ReSAC reduces refresh and communication overheads by 7–100
 % and 53–75%, respectively, leading to a 1.12× to 2.02× latency reduction 
 across low-batch LLM inference workloads.\n\nTopics: Quantum\n\nTrack: DES
 6. Quantum Computing, Systems\n\nSession Chairs: Hokeun Kim (Arizona State
  University); BaekGyu Kim (Daegu Gyeongbuk Institute of Science and Techno
 logy); Xiang Chen (Peking University); Sangyeob Kim (Yonsei University); R
 obert M. Radway (University of Pennsylvania); Prashanth Mohan (University 
 of Pittsburgh); Xiaoxuan Yang (University of Virginia, Stanford University
 ); Ramtin Zand (University of South Carolina); Hadi Kamali (University of 
 Central Florida); Jiafeng Xie (Villanova University); Prabuddha Chakrabort
 y (University of Maine); Junichiro Kadomoto (University of Tokyo); and Yos
 uke Ueno (RIKEN)\n\n
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