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UID:dac_DAC 2026_sess315_RESEARCH1412@linklings.com
SUMMARY:Reconfigurable 3D-VRRAM LUT-CiM with Greedy G-shuffle Quantization
  for End-to-End 4-bit ViTs in Edge Dense Prediction
DESCRIPTION:Yi Li and Zijian Ye (The University of Hong Kong); Zhaori Cong
  and Shengzhe Yan (Institute of Computing Technology, CAS); Songqi Wang (T
 he university of Hong Kong); Ning Lin (The University of Hong Kong); Jinsh
 an Yue (Institute of Computing Technology, CAS); xiaojuan qi (University o
 f Hong Kong); Zhongrui Wang (Southern University of Science and Technology
 ); and Han Wang (The University of Hong Kong)\n\nThe rise of embodied inte
 lligence is driving the deployment of Vision Transformers (ViTs) for dense
  prediction (DP) tasks on resource-limited edge devices. Look-up-table (LU
 T)-based digital compute-in-memory (CiM) has emerged as a promising paradi
 gm, delivering high accuracy with superior energy and area efficiency. How
 ever, practical ViT deployment on LUT‑CiM for edge DP  faces dual hardware
  and software challenges: (1) LUT cost scales exponentially with bit-width
 , while NLP‑oriented quantization struggles to push convolution-heavy ViTs
  below 8 bits, especially in compact on‑chip CiM models; and (2) fixed LUT
  structures cannot accommodate ViTs' heterogeneous static/dynamic workload
 s, while unstructured mixed‑precision weights strain memory density and ut
 ilization. To overcome these, we propose a software-hardware co-designed l
 ow-precision ViT accelerator.  Software-wise, we propose Greedy G-shuffle,
  a lightweight, general quantization method, paired with a PCA‑based, chan
 nel‑wise weight assignment, tailored for lightweight ViTs in edge DP tasks
 . Hardware-wise, at the architectural level, we introduce a reconfigurable
  LUT-based CiM macro that accelerates both static and dynamic matrix opera
 tions with superior energy efficiency, complemented by a high-utilization 
 pipeline- and tensor-parallel dataflow that serves heterogeneous ViT layer
 s. At the circuit level, we employ high-density 1TnR VRRAM with flexible r
 ead paths and channel-wise hardware remapping to support mixed-precision I
 NT4/2/1 weights, minimizing area overhead. We demonstrate the first fully 
 4-bit ViT with INT4 activations and structured INT4/2/1 weights on a recon
 figurable 3D 1TnR VRRAM LUT-based CiM macro, achieving a 26.7% improvement
  in mIoU and a 30.1% reduction in RMSE on the ADE20K and NYUDv2 compared t
 o vanilla round-to-nearest quantization, along with up to 8.9× area effici
 ency and 9.7× energy efficiency improvements over the state-of-the-art.\n\
 nTopics: Quantum\n\nTrack: DES6. Quantum Computing, Systems\n\nSession Cha
 irs: Hokeun Kim (Arizona State University); BaekGyu Kim (Daegu Gyeongbuk I
 nstitute of Science and Technology); Xiang Chen (Peking University); Sangy
 eob Kim (Yonsei University); Robert M. Radway (University of Pennsylvania)
 ; Prashanth Mohan (University of Pittsburgh); Xiaoxuan Yang (University of
  Virginia, Stanford University); Ramtin Zand (University of South Carolina
 ); Hadi Kamali (University of Central Florida); Jiafeng Xie (Villanova Uni
 versity); Prabuddha Chakraborty (University of Maine); Junichiro Kadomoto 
 (University of Tokyo); and Yosuke Ueno (RIKEN)\n\n
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