BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260730T152650Z
LOCATION:
DTSTART;TZID=America/Los_Angeles:20260728T123000
DTEND;TZID=America/Los_Angeles:20260728T130000
UID:dac_DAC 2026_sess315@linklings.com
SUMMARY:RM Poster Session Four
DESCRIPTION:E³-CODE: Embedded and Efficient Error-Correcting Code for Erro
 r-Resilient Neural Networks\n\nNeural networks are widely deployed at the 
 edge to process high-\ndimensional sensor data, but they are susceptible t
 o burst errors that\ncan corrupt weights and degrade inference accuracy. C
 onventional\nerror-correcting codes (ECC) mitigate errors but incur signif
 icant\nmemory overhead. Recent ECC meth...\n\n\nVenkata Nithin Kamineni, H
 abibur Rahaman, Ovishake Sen, Baibhab Chatterjee, SWARUP BHUNIA, and Ricka
 rd Ewetz (University of Florida)\n---------------------\nSliceMoE: Bit-Sli
 ced Expert Caching under Miss-Rate Constraints for Efficient MoE Inference
 \n\nMoE models offer efficient scaling through conditional computation, bu
 t their large parameter size and expensive expert offloading make on-devic
 e deployment challenging. Existing acceleration techniques such as prefetc
 hing or expert clustering often increase energy usage or reduce expert div
 ersity. ...\n\n\nYuseon Choi, Sangjin Kim, Jungjun Oh, Gwangtae Park, Byeo
 ngcheol Kim, and Hoi-Jun Yoo (Korea Advanced Institute of Science and Tech
 nology (KAIST))\n---------------------\nTowards Always-on Interaction: A S
 ub-mW Visual Wakeup Acceleration Subsystem for Smart Glasses\n\nAlways-on 
 vision is essential for smart glasses, yet continuous visual-processing un
 der stringent power budgets remains a major challenge. This work presents 
 an always-on visual wakeup acceleration-engine for sub-milliwatt hand gest
 ure recognition. A compact convolutional neural network (<13k parame...\n\
 n\nArpan Suravi Prasad, Sergio Mazzola, and Cyrill Durrer (ETH Zürich); Da
 vide Rossi (University Of Bologna); Francesco Conti (University of Bologna
 ); and Luca Benini (Università di Bologna and ETH Zurich)\n---------------
 ------\nPAGE: Processing-Using-DRAM Architecture-Circuits Co-Optimization 
 for Efficient Acceleration of General Matrix-Vector Multiplication\n\nAs l
 arge language models (LLMs) continue to scale in size and complexity, DRAM
  access has become a performance bottleneck, especially during the memory-
 bound decoding phase dominated by general matrix-vector multiplication (GE
 MV) operations. Recent work has explored near-/in-memory computing to addr
 ...\n\n\nYifan He and Hyung Joon Byun (Cornell University); Jimin Lee (SK 
 hynix); Do-Yoon Lim (Cornell University); Houxiang Ji, Jungmin Choi, and H
 oshik Kim (SK hynix); and Jae-sun Seo (Cornell University)\n--------------
 -------\nDeTrojan: Detecting Trojan Circuits Using a Purpose-Built Graph N
 eural Network with Community-Enhanced Classification\n\nGate-level Hardwar
 e Trojan (HT) detection using Graph Neural Networks (GNNs) often suffers f
 rom limited accuracy due to the reliance on structure-only features and fr
 agmented node-level predictions. We propose a GNN-based framework, \papert
 itle, to overcome these challenges through three key innovat...\n\n\nChien
 -Tung (Cherie) Kuo, Chen-Ching Nieh, Jie-Hong Roland Jiang, and Chung-Yang
  (Ric) Huang (National Taiwan University)\n---------------------\nShooting
  Falcon with One Fault: A Practical Rowhammer-based Fault Attack against F
 alcon\n\nFalcon, a compact post-quantum digital signature scheme, has been
  selected by National Institute of Standards and Technology (NIST) for the
  standardization of post-quantum cryptography. While it effectively mitiga
 tes the emerging quantum threats, its susceptibly to fault attacks remains
  insufficient...\n\n\nZihao Xin (Zhejiang University); Xin Zhang (Peking U
 niversity); Zhe Liu and Qianmei Wu (Zhejiang University); Qingni Shen (Pek
 ing University); Ruyi Ding (Louisiana State University); Yixin Jiang, Wenq
 ian Xu, and Zhihong Liang (CSG Electric Power Research Institute Co., Ltd)
 ; Lu Zhou (Nanjing University of Aeronautics and Astronautics); and Fan Zh
 ang (Zhejiang University; Key Laboratory of Blockchain and Cyberspace Gove
 rnance of Zhejiang Province; Alibaba-Zhejiang University Joint Research In
 stitute of Frontier Technologies;ZJU-Hangzhou Global Scientific and Techno
 logical Innovation Center; Jiaxing Research Institute, Zhejiang University
 )\n---------------------\nEPAR: Electromagnetic Pathways to Architectural 
 Reliability in Quantum Processors\n\nAs superconducting processors scale, 
 understanding how physical layout shapes qubit interactions is essential f
 or architectural reliability. Existing methods offer limited insight into 
 how electromagnetic design choices translate into execution-level behavior
 . We present EPAR, an electromagnetic-to-...\n\n\nNavnil Choudhury (Rensse
 laer Polytechnic Institute), Yizhuo Tan (Yale University), Jiaqi Yu and Ja
 kub Szefer (Northwestern University), and Kanad Basu (RPI)\n--------------
 -------\nFrom Characterization to Microarchitecture: Designing an Elegant 
 and Reliable BFP-Based NPU\n\nBFP is emerging as an attractive data format
  for edge NPUs, combining wide dynamic range with high hardware efficiency
 . However, its behavior under hardware faults and its suitability for safe
 ty-critical deployments remain largely underexplored. Here, we present the
  first in-depth empirical reliabil...\n\n\nJie Zhang (Southeast University
 ), Jiapeng Guan and Hao Zhou (Dalian University of Technology), Xiaomeng H
 an and Tinglue Wang (Southeast University), Ran Wei (Lancaster University)
 , and Zhe Jiang (South East University)\n---------------------\nDAPA: Dist
 ribution Aware Piecewise Activation Functions for On-Device Transformer In
 ference and Training\n\nNon-linear activation functions play a pivotal rol
 e in on-device inference and training, as they not only consume substantia
 l hardware resources but also impose a significant impact on system perfor
 mance and energy efficiency.\nIn this work, we propose Distribution-Aware 
 Piecewise Activation (DAPA), ...\n\n\nMaoyang Xiang and Bo Wang (Singapore
  University of Technology and Design)\n---------------------\nHeRo: Adapti
 ve Orchestration of Retrieval-Augmented Generation on Heterogeneous Mobile
  SoC\n\nHeRo is a framework for efficiently running agentic RAG on resourc
 e-limited, heterogeneous mobile devices. It builds a performance model tha
 t accounts for workload, accelerator features, and memory contention, then
  uses a lightweight, dependency-guided scheduler with shape-aware decompos
 ition, criti...\n\n\nMaoliang Li, Jiayu Chen, and Zihao Zheng (Peking Univ
 ersity); Ziqian Li (Northwestern Polytechnical University); Xinhao Sun and
  Guojie Luo (Peking University); Chenchen Liu (Beihang University); and Xi
 ang Chen (Peking University)\n---------------------\n3D-ReSAC: A Near-3D-S
 tacked-DRAM Processor with Area-Efficient Sequential Refresh-Skip and High
 -Link-Utilization ArrowMesh Communication for Fast Low-batch LLM Inference
 \n\nLow-batch LLM inference on edge hardware places stringent demands on b
 oth memory bandwidth and computational capacity. While 3D-stacked DRAM acc
 elerators offer a promising solution, they introduce two critical overhead
 s that are frequently under-optimized: DRAM refresh and collective communi
 cation.\n...\n\n\nWenbin Jia and Haocheng Li (Tsinghua University), Xiang 
 Li (Tsinghua), and Xinyuan Lin and Yongpan Liu (Tsinghua University)\n----
 -----------------\nReConnaissance: Correctly Tracking Multiple Secrets usi
 ng Reveal/Conceal Paradigms\n\nSecure speculation schemes are critical for
  defeating speculative side-channel attacks, but often incur notable perfo
 rmance penalties, encouraging research into optimization strategies. One s
 uch optimization strategy, ReCon, improves performance by exploiting previ
 ous non-speculative data leakage to...\n\n\nAmund Bergland Kvalsvik and Ma
 gnus Sjalander (Norwegian University of Science and Technology)\n---------
 ------------\nCapacitive Touchscreens at Risk: Recovering Handwritten Traj
 ectory on Smartphone via Electromagnetic Emanations\n\nThis paper reveals 
 and exploits a critical security vulnerability: the electromagnetic (EM) s
 ide channel of capacitive touchscreens leaks sufficient information to rec
 over fine-grained, continuous handwriting trajectories. We present Touchsc
 reen Electromagnetic Side-channel Leakage Attack (TESLA), a...\n\n\nYukun 
 Cheng, Shiyu Zhu, and Changhai Ou (Wuhan University); Xingshuo Han (Nanjin
 g University of Aeronautics and Astronautics); Yuan Li (National Universit
 y of Defense Technology); and Shihui Zheng (Beijing University of Posts an
 d Telecommunications)\n---------------------\nProvably Probabilistic Safe 
 Controller Synthesis for Vision-Based Neural Network Control Systems\n\nTh
 e prevalence of nonlinear systems in safety-critical domains calls for con
 trollers with safety guarantees, while vision-based control relies on high
 -dimensional images complicates both decision-making and formal safety ana
 lysis under uncertainty. This paper proposes a provably safe controller sy
 nt...\n\n\nQianlong Hu, Hanrui Zhao, and Liqian Chen (National University 
 of Defense Technology); Zhengfeng Yang (East China Normal University); and
  Banghu Yin and Ji Wang (National University of Defense Technology)\n-----
 ----------------\nAn Energy-Efficient Dataflow Architecture for Efficient 
 MoE Model Inference\n\nThe Mixture-of-Experts (MoE) model sparsely activat
 es a subset of experts for each token, causing each expert to process a va
 rying number of tokens during inference. However, existing GPU-based MoE i
 nference frameworks adopt a fixed tensor size for the inputs to each exper
 t, requiring padding when a...\n\n\nKexin Li, Qinggang Wang, Chuanhui Qi, 
 Shaoxian Xu, and Wenkan Huang (Huazhong University of Science and Technolo
 gy); Xiangzheng Yang (Zhengzhou University); ruoshi li (Huazhong Universit
 y of Science and Technology); Bo Liu (Zhengzhou University); and Long Zhen
 g, Xiaofei Liao, and Hai Jin (Huazhong University of Science and Technolog
 y)\n---------------------\nLearning the "Why": Causal-Aware Learning in Ex
 plainable and Efficient CPU Design Optimization\n\nAs modern CPUs grow inc
 reasingly configurable, design space exploration (DSE) has become essentia
 l for navigating complex architectural trade-offs. However, existing DSE a
 pproaches predominantly rely on statistical correlations, resulting in opa
 que decision processes. They cannot clearly explain the...\n\n\nYiyang Zha
 o, Tianning Gao, Hongyang Pan, Liangji Wu, Yiming Wei, Zhaori Bi, Changhao
  yan, and Xuan Zeng (Fudan University)\n---------------------\nAchieving I
 ntra- and Inter-Operator Communication Lower Bounds in Near-Memory Process
 ing\n\nNear-memory processing (NMP) is a promising way to overcome the mem
 ory wall in large language models (LLMs). However, dataflow optimization i
 n NMP is fundamentally constrained, as existing analyses cannot efficientl
 y handle the new distributed vault/channel organization. We propose the Re
 mote-Access...\n\n\nLei Xu, Chen Yin, Zelong Yuan, Weiguang Sheng, Jianfei
  Jiang, Qin Wang, and Naifeng Jing (Shanghai Jiao Tong University)\n------
 ---------------\nNetDeTox: Adversarial and Efficient Evasion of Hardware-S
 ecurity GNNs via RL-LLM Orchestration\n\nGraph neural networks (GNNs) are 
 widely used in hardware security but vulnerable to adversarial netlist rew
 rites. Existing adversarial approaches incur high overheads. We present Ne
 tDeTox, an automated framework combining large language models (LLMs) with
  reinforcement learning (RL) for efficient re...\n\n\nZeng Wang and Mingha
 o Shao (New York University); Akashdeep Saha (New York University, Abu Dha
 bi); Ramesh Karri (NYU); and Johann Knechtel, Muhammad Shafique, and Ozgur
  Sinanoglu (New York University, Abu Dhabi)\n---------------------\nExploi
 ting Per-Core Leakage: Electromagnetic Side-Channel Monitoring of Multicor
 e Architectures\n\nMulticore processors are increasingly adopted in embedd
 ed systems to meet growing performance demands. However, physical side-cha
 nnel analysis of multicore architectures remains underexplored, as obtaini
 ng usable leakage is inherently challenging. Consequently, side-channel se
 curity research on such...\n\n\nDaehyeon Bae, Sujin Park, and Insup Lee (K
 orea University); Young-Giu Jung (YM-NaeulTech); Kyeongsik Lee (Agency for
  Defense Development); Heeseok Kim (Korea University); and Seokhie Hong (I
 ndependent Researcher)\n---------------------\nCryoZip: An Efficient Cryog
 enic Compressor for Quantum Error Correction Syndromes\n\nScaling fault-to
 lerant quantum computing is increasingly constrained by the limited bandwi
 dth and power budget across the 4\,K-room temperature (RT) interface. We p
 resent CryoZip, a cross-layer cryogenic compression framework that coopera
 tes with an lightweight in-house quantum error correction (QEC...\n\n\nGua
 nchen Tao, Alexander Knapen, Jacob Mack, Gokul Subramanian Ravi, and Qirui
  Zhang (University of Michigan); Mehdi Saligane (Brown University); and De
 nnis Sylvester (University of Michigan)\n---------------------\nWINNER: A 
 Wireless In-Vivo/Ex-Vivo Runtime Analyzer for Intermittent Computing\n\nIn
 termittent computing systems suffer from limited observability and lack ef
 fective runtime analysis mechanisms. Unlike conventional systems, they are
  vulnerable not only to typical programming errors but also to a distinct 
 class of failures known as \textit{intermittence bugs}, which emerge due t
 o ...\n\n\nJustin Feng (University of California, Los Angeles); Arman Rooh
 i (University of Illinois Chicago); and Nader Sehatbakhsh (University of C
 alifornia, Los Angeles)\n---------------------\nHBSpec: A Hybrid-Bonding-b
 ased Heterogeneous Accelerator for Efficient Tree-Structured Speculative D
 ecoding\n\nWe propose HBSpec, a hybrid-bonding (HB)-based heterogeneous ac
 celerator for tree-based speculative LLM inference. Unlike existing near-m
 emory processing (NMP)-enabled heterogeneous accelerators that place proce
 ssing elements (PEs) on DRAM dies with limited computation capability, HBS
 pec customizes ...\n\n\nRunze Wang, Qinggang Wang, Haifeng Liu, Xinyu Zhu,
  Chenggang Duan, Long Zheng, Xiaofei Liao, and Hai Jin (Huazhong Universit
 y of Science and Technology) and Jingling Xue (UNSW)\n--------------------
 -\nHybrid PIM-oriented Architecture-Dataflow Co-Design for Heterogeneous L
 LM Inference\n\nRecent studies show that incorporating Processing-in-Memor
 y (PIM) into neural processing units (NPUs) can significantly improve the 
 efficiency of large language model (LLM) inference on edge devices.\nHowev
 er, the limited compute capability of DRAM-PIM and the use of fixed datafl
 ow strategies still c...\n\n\nHai Huang and Feng Qiu (Beihang University),
  Xiang Chen (Peking University), and Weisheng Zhao and Chenchen Liu (Beiha
 ng University)\n---------------------\nReconfigurable 3D-VRRAM LUT-CiM wit
 h Greedy G-shuffle Quantization for End-to-End 4-bit ViTs in Edge Dense Pr
 ediction\n\nThe rise of embodied intelligence is driving the deployment of
  Vision Transformers (ViTs) for dense prediction (DP) tasks on resource-li
 mited edge devices. Look-up-table (LUT)-based digital compute-in-memory (C
 iM) has emerged as a promising paradigm, delivering high accuracy with sup
 erior energy and...\n\n\nYi Li and Zijian Ye (The University of Hong Kong)
 ; Zhaori Cong and Shengzhe Yan (Institute of Computing Technology, CAS); S
 ongqi Wang (The university of Hong Kong); Ning Lin (The University of Hong
  Kong); Jinshan Yue (Institute of Computing Technology, CAS); xiaojuan qi 
 (University of Hong Kong); Zhongrui Wang (Southern University of Science a
 nd Technology); and Han Wang (The University of Hong Kong)\n--------------
 -------\nPD-Net: Learning Device-Invariant Representations for Heterogeneo
 us Cross-Device Side-Channel Attacks\n\nHeterogeneous cross-device side-ch
 annel attacks remain a critical yet underexplored challenge, as models tra
 ined on one device often fail to generalize across architectures. This pap
 er presents PD-Net, a domain generalization framework that learns device-i
 nvariant features by disentangling algorithm...\n\n\nDalin He, Wei Cheng, 
 Yuejun Liu, Jingdian Ming, and Yongbin Zhou (Nanjing University of Science
  and Technology)\n---------------------\nTRAC: Transparent Row Activation 
 Counting for Efficient RowHammer Monitoring\n\nRowHammer is one of the mos
 t critical security threats in modern DRAM. The industry has introduced Pe
 r-Row Activation Counting (PRAC) to monitor activations, but this approach
  degrades performance by lengthening critical DRAM timing parameters. We p
 ropose TRAC (Transparent Row Activation Counting), ...\n\n\nSunggi Ahn (Su
 ngkyunkwan University), Saeid Gorgin (SKKU), and Jungrae Kim (Sungkyunkwan
  University)\n---------------------\nSiTA: Exploiting Sparsity in Tensor-P
 roduct for Accelerating Quantum Readout Error Mitigation\n\nThough quantum
  computing theoretically provides exponential computational advantage, an 
 end-to-end quantum speedup should consider the encoding, compilation, and 
 many other peripheral process that rely on classical computer. Among them,
  the readout error mitigation turns out to be the bottleneck, re...\n\n\nH
 anyu Zhang (Zhejiang University); Zhiwei Ye (China Mobile (Suzhou) Softwar
 e Technology); Liqiang Lu, Kaiwen Zhou, Fangxu Guo, and Siwei Tan (Zhejian
 g University); Fangxin Liu (Shanghai Jiao Tong University); Size Zheng (Ts
 inghua University); and Jianwei Yin (Zhejiang University)\n---------------
 ------\nEnergyHDC: Intermittent Hyperdimensional Inference on Energy-Harve
 sting IoT\n\nAmbient energy harvesting technologies offer the promise of p
 erpetual operation for batteryless Internet of Things (IoT) devices; howev
 er, their execution is frequently halted by unpredictable power failures. 
 Traditional methods to ensure correctness, such as software checkpointing 
 (e.g., Mementos) ...\n\n\nYUSHENG LIU (National Yang Ming Chiao Tung Unive
 rsity (NYCU)) and Yong-Cheng Liaw and Shuo-Han Chen (National Yang Ming Ch
 iao Tung University)\n---------------------\nCAPA: Convertibility-Aware Mi
 xed-Precision Accelerator for Asymmetric GEMM in Weight-Only Quantized LLM
 s\n\nFP-INT GEMM accelerators for weight-only quantized large language mod
 els suffer from large partial sum (psum) overhead and a lack of precision-
 convertibility, limiting scalability. To mitigate this, we propose CAPA, a
 n accelerator achieving high efficiency and versatility. (1) CAPA introduc
 es Hybrid...\n\n\nJihyun Moon, Insu Choi, Seungchan Lee, and Joon-Sung Yan
 g (Yonsei University)\n---------------------\nGREEN: Towards Scalable Ener
 gy-Efficient Workload Scheduling and Placement in the Cloud\n\nThe workloa
 d scheduling and placement problem has been the core of resource managemen
 t in various distributed systems, including modern cloud computing systems
 . As modern cloud systems become larger, more heterogeneous, dynamic, comp
 licated, and energy-hungry, developing a scalable, flexible, adapti...\n\n
 \nJinghua Wang (University of Illinois Urbana-Champaign); Asser Tantawi, O
 livier Tardieu, Alaa Youssef, Tamar Eilam, Chen Wang, and Pradip Bose (IBM
  Research); JIAXIN WAN and Klara Nahrstedt (University of Illinois Urbana-
 Champaign); and Deming Chen (UIUC)\n---------------------\nKeeping PIM Bus
 y: Eliminating Execution Overheads for Full Throughput\n\nLarge language m
 odels (LLMs), such as GPT-3 and Llama-2, impose extreme memory-bandwidth d
 emands, creating severe data movement bottlenecks. Processing-in-Memory (P
 IM) mitigates this by performing computations near memory; however, curren
 t PCIe-based PIM systems deliver only a small fraction of thei...\n\n\nMun
  Seong Park, Jisung Pack, Junil Kim, Jun Sik Kim, Seok Young Kim, and Seon
  Kim (Korea University)\n---------------------\nAutomated Discovery, Class
 ification, and Systematic Security Verification Methodology for Undocument
 ed Instructions\n\nUndocumented instructions pose a growing security threa
 t, yet current research is limited. \nExisting work focuses on discovery w
 ith constrained techniques, while semantic analysis is manual and ad-hoc. 
 Moreover, a significant gap exists in methodologies for systematic securit
 y verification. This pap...\n\n\nYooseok Lee and Junho Jo (Kangwon Nationa
 l University), Hanjoon Kim (Furiosa AI), and Wonjun Song (Kangwon National
  University)\n---------------------\nSLCross: Cross-Component System-Level
  Cache Side-Channel Attacks on Apple M2 SoC\n\nCross-component cache side-
 channel attacks exploit shared cache resources across different processing
  units to infer sensitive information, posing a significant threat to mode
 rn heterogeneous computing systems. However, the effectiveness of fine-gra
 ined cache attacks across components on Apple silic...\n\n\nYakun Wu, Guan
 long Wu, Yusi Feng, and Yinqian Zhang (Southern University of Science and 
 Technology)\n---------------------\nLUNA: LUT-Based Neural Architecture fo
 r Fast and Low-Cost Qubit Readout\n\nQubit readout is a critical operation
  in quantum computing systems, which maps the analog response of qubits in
 to discrete classical states. Deep neural networks (DNNs) have recently em
 erged as a promising solution to improve readout accuracy . Prior hardware
  implementations of DNN-based readout are...\n\n\nMuhammad Ali Farooq (Ari
 zona State University), Giuseppe Di Guglielmo (Fermi National Accelerator 
 Laboratory), Abhi Rajagopala (University of Arkansas), Nhan Tran (Fermi Na
 tional Accelerator Laboratory), and Vidya A. Chhabria and Aman Arora (Ariz
 ona State University)\n---------------------\nLLM-Enhanced Two-Stage Signa
 l Temporal Logic Automatic Transformation with Structured Intermediate Rep
 resentation\n\nSignal Temporal Logic (STL) is a formal specification langu
 age for describing real-time and real-valued properties of Cyber-Physical 
 Systems (CPS).Accurate and automatic translation of CPS specifications in 
 natural language (NL) into formal STL formulas is crucial. Traditional met
 hods relying on man...\n\n\nHongjing Qing (Institute of Software, Chinese 
 Academy of Sciences; University of Chinese Academy of Sciences) and Jie An
  and Fanjiang Xu (Institute of Software, Chinese Academy of Sciences)\n---
 ------------------\nCORE: Compact, Optimized, and Resource-Efficient Compu
 te Engine for FP-INT GEMM Acceleration with Binary Coding Quantization\n\n
 Recent advances in large language models (LLMs) have driven exponential gr
 owth in parameter counts, amplifying memory footprints and creating acute 
 computational bottlenecks. \nWeight-only quantization is a common mitigati
 on because weights dominate storage and incur less accuracy degradation th
 an ac...\n\n\nChaewon Park, Inseong Hwang, Beom Jin Kang, and Hyun Kim (Se
 oul National University of Science and Technology)\n---------------------\
 nUniSpike: Accelerating Spiking Neural Networks on Neuromorphic Systems vi
 a Eliminating Address Redundancy\n\nMany-core neuromorphic systems serve a
 s specialized accelerators for Spiking Neural Networks (SNNs). However, th
 e communication mechanisms in existing neuromorphic systems incur signific
 ant traffic and energy overhead due to redundant address transmissions, a 
 bottleneck exacerbated by the short payl...\n\n\nQinghui Xing, Zhuo Chen, 
 Xin Du, Ouwen Jin, Ming Zhang, Pan Lv, Ying Li, Shuiguang Deng, and Gang P
 an (Zhejiang University)\n---------------------\nMaple: Efficient Data-Tra
 nsfer-Aware Mapping Exploration for NDP-enabled Edge LLM Inference\n\nNear
 -DRAM Processing (NDP) has demonstrated great \n    potential for memory-b
 ound \n    operators in edge-side large language model (LLM) inference.\n 
    Featuring a xPU-NDP heterogeneous system, \n    existing designs concen
 trate on optimizing the execution flow \n    within processing units, \n  
   yet ...\n\n\nXuefeng Hua and Cong Li (Peking University), Xin Si (Southe
 ast University), Qiang Wu (Houmo AI), and Guangyu Sun (Peking University)\
 n---------------------\nNothing Left to Learn: Isomorphic Graph Transforma
 tions for Hardware IP Protection\n\nLogic locking protects hardware design
 s across the global semicon-\nductor supply-chain. However, recent machine
  learning (ML)-based\nattacks, especially graph learning-based ones, have 
 undermined\nits security by learning circuit structures and gate compositi
 ons to\nreveal locked connections/gates. Alt...\n\n\nShaza Elsharief (New 
 York University, Abu Dhabi); Lilas Alrahis (Khalifa University); and Johan
 n Knechtel and Ozgur Sinanoglu (New York University, Abu Dhabi)\n---------
 ------------\nMistleTunnel: Attacking KASLR on Apple M-Series Silicon with
  a Novel TLB Side Channel\n\nKASLR is a critical defense on macOS, whose i
 mplementation on M-series silicon and the latest macOS is further strength
 ened by hardware–software mitigations, with no practical bypass. We perfor
 m a systematic reverse-engineering of the TLB on M-series silicon and unco
 ver a novel user–kern...\n\n\nHanyin Liu, Jin Wu, and Rihui Sun (Harbin In
 stitute of Technology); Kaiyuan Rong and Hongpei Zheng (Tsinghua Universit
 y); Yun Chen (Hong Kong University of Science and Technology (HKUST)); Jia
 n Dong (Harbin Institute of Technology); and Dongsheng Wang (Tsinghua Univ
 ersity)\n---------------------\nNIAQ: Adaptive Non-Ideality-Aware Qubit Re
 adout for Long-Term Accuracy\n\nHigh-accuracy qubit-state readout is criti
 cal for quantum computation. While existing hardware-based qubit-state dis
 criminators assume stable readout statistics across measurement shots, rea
 listic long-running tasks like chemistry simulation suffer from slow noise
  fluctuations and drift that severel...\n\n\nYuyang Du (Nanyang Technologi
 cal University); Yi Sheng Chong (Institute of Microelectronics, Agency for
  Science, Technology and Research); Wang Ling Goh (Nanyang Technological U
 niversity); Benjamin Lienhard (Technical University of Munich); and Anh Tu
 an Do (Institute of Microelectronics, Agency for Science, Technology and R
 esearch)\n---------------------\nTorR: Towards Brain-Inspired Task-Oriente
 d Reasoning via Cache-Oriented Algorithm-Architecture Co-design\n\nTask-or
 iented object detection on CLIP enables open-vocabulary, prompt-driven sem
 antics but dense alignment and memory traffic block real-time edge use. We
  propose TorR, a brain-inspired algorithm–architecture co-design that repl
 aces CLIP-style dense matching with hyperdimensional associative reason...
 \n\n\nHyunwoo Oh (University of California, Irvine); SungHeon Jeong (UCI);
  Suyeon Jang, Hanning Chen, Sanggeon Yun, and Tamoghno Das (University of 
 California, Irvine); and Mohsen Imani (University of California Irvine)\n-
 --------------------\nREACT: Rapid Error-Tolerant Activation Compressor fo
 r Efficient Transformer Training\n\nTraining large language models (LLMs) 
 poses considerable challenges due to long training times, extensive memory
  requirements, and substantial bandwidth demands. Activation compression i
 s a promising approach to reduce the memory footprint since activation mem
 ory accounts for the majority of memory ...\n\n\nSeungyong Lee, Geonu Yun,
  Xuan Truong Nguyen, and Hyuk-Jae Lee (Seoul National University)\n-------
 --------------\nLHGstore: An In-Memory Learned Graph Storage for Fast Upda
 tes and Analytics\n\nVarious real-world applications rely on in-memory dyn
 amic graphs that must efficiently handle frequent updates while supporting
  low-latency analytics on evolving structures. Achieving both objectives r
 emains challenging due to the trade-off between update efficiency and trav
 ersal locality, particula...\n\n\nPengpeng Qiao (Institute of Science Toky
 o), Zhiwei Zhang and Xinzhou Wang (Beijing Institute of Technology), Zheta
 o Li (Jinan University), Xiaochun Cao (Sun Yat-sen University), and Yang C
 ao (Institute of Science Tokyo)\n---------------------\nTriMoE: Augmenting
  GPU with AMX-Enabled CPU and DIMM-NDP for High-Throughput MoE Inference v
 ia Offloading\n\nTo deploy large Mixture-of-Experts (MoE) models cost-effe
 ctively, offloading-based single-GPU heterogeneous inference is crucial. W
 hile GPU–CPU architectures that offload cold experts are constrained by ho
 st memory bandwidth, emerging GPU-NDP architectures utilize DIMM-NDP to of
 fload non-hot experts...\n\n\nYudong Pan (CICS, Institute of Computing Tec
 hnology, Chinese Academy of Sciences;University of Chinese Academy of Scie
 nces;); Yintao He (State Key Laboratory of Computer Architecture, Institut
 e of Computing Technology, Chinese Academy of Sciences); Tianhua Han (Inst
 itute of Computing Technology, CAS); Lian Liu (Institute of Computing Tech
 nology); Shixin Zhao (Chinese Academy of Sciences); Zhirong Chen (Research
  Center for Intelligent Computing System, Institute of Computing Technolog
 y, Chinese Academy of Sciences); Mengdi Wang and Cangyuan Li (Institute of
  Computing Technology, Chinese Academy of Sciences); yinhe han (Institute 
 of Computing Technology, CAS); and Ying Wang (State Key Laboratory of Comp
 uter Architecture, Institute of Computing Technology, Chinese Academy of S
 ciences)\n---------------------\nDecoding the Past: Recovering Sensitive D
 ata from SRAM Aging Imprints\n\nLong-term data remanence in SRAMs can pose
  serious security risks when discarded ICs retain sensitive information. U
 nlike DRAM and Flash memories, SRAMs have been largely overlooked in this 
 field due to their very short retention periods. Prior works demonstrated 
 that aging-induced imprints enable p...\n\n\nZakia Tamanna Tisha and Gaine
 s Odom (Auburn University), Biswajit Ray (Colorado State University), and 
 Ujjwal Guin (Auburn University)\n---------------------\nStone-Skimming: At
 tacking Big-Data Analytics Applications with Page Table Walk\n\nThis paper
  proposes the Stone-Skimming microarchitectural attack, the first page tab
 le walk (PTW)-based attack targeting large-scale sensitive memory applicat
 ions. Stone-Skimming leverages the correlation among multiple signals to e
 stablish novel side channel attacks. We develop the first microarchi...\n\
 n\nJiajun Luo and Yu Jin (Tsinghua University); Yufeng Gu (University of M
 innesota); and Jinyi Deng, Yang Hu, and Shuwen Deng (Tsinghua University)\
 n---------------------\nHighly-Parallel Atom-Detection Accelerator for Twe
 ezer-Based Neutral Atom Quantum Computers\n\nNeutral atom quantum computer
 s (NAQCs) are among the most promising computational platforms for quantum
  computing. Controlling and measuring individual atoms and their states, w
 hich often requires multiple imaging and image-analysis procedures, is typ
 ically the most time-consuming task during comput...\n\n\nJonas Winklmann 
 (Technical University of Munich), Yian Yu (Ludwig-Maximilians-Universität 
 München), Xiaorang Guo (Technical University of Munich), Korbinian Staudac
 her (Ludwig-Maximilians-Universität München), and Martin Schulz (Technical
  University of Munich)\n---------------------\nHyperLiDAR: Adaptive Post-D
 eployment LiDAR Segmentation via Hyperdimensional Computing\n\nLiDAR seman
 tic segmentation plays a pivotal role in scene understanding for edge appl
 ications such as autonomous driving. Once deployed in the real world, the 
 model must adapt to its surrounding environment through rapid adaptive tra
 ining and updates, even with limited compute and energy resources\no...\n\
 n\nIvannia Gomez Moreno, Yi Yao, and Ye Tian (University of California, Sa
 n Diego); Xiaofan Yu (University of California Merced); Flavio Ponzina (Sa
 n Diego State University); Michael Sullivan and Jingyi Zhang (University o
 f California, San Diego); Mingyu Yang and Hun Seok Kim (University of Mich
 igan); and Tajana Rosing (University of California, San Diego)\n----------
 -----------\nHiBand: A Hierarchical Bandwidth-Aware HB-DRAM Accelerator wi
 th Array-Level Co-Execution and Reconfigurable NoC for LLM Inference\n\nHy
 brid-bonding 3D DRAM (HB-DRAM) delivers massive in-situ bandwidth but shif
 ts LLM accelerator bottlenecks from off-chip memory to the Network-on-Chip
 , where decentralized bank-local bandwidth must be coordinated across arra
 ys. We present HiBand, a bandwidth-aware HB-DRAM accelerator that co-desig
 ns...\n\n\nHuanyu Wang, Yang Wang, Yutong Su, Jiaxin Yang, Yang Hu, and Sh
 ouyi Yin (Tsinghua University)\n---------------------\nScalable and Adapti
 ve Parallel Training of Graph Transformer on Large Graphs\n\nGraph foundat
 ion models have demonstrated remarkable adaptability across diverse downst
 ream tasks through large-scale pretraining on graphs. However, existing im
 plementations of the backbone model, graph transformers, are typically lim
 ited to single-GPU systems, leading to long training times or out...\n\n\n
 Jun-Liang Lin and Kamesh Madduri (Pennsylvania State University) and Mahmu
 t Kandemir (PSU)\n---------------------\nNVLLM: A 3D NAND-Centric Architec
 ture Enabling Edge on-Device LLM Inference\n\nThe rapid growth of LLMs dem
 ands high-throughput, memory-capacity–intensive inference on resource-cons
 trained edge devices, where single-batch decoding remains fundamentally me
 mory-bound. Existing out-of-core GPUs and SSD-like accelerators are limite
 d by DRAM-bound weight movement and inefficient st...\n\n\nMingbo Hao, Cha
 ngwei Yan, Haoyu Cui, Zhihao Yan, Yizhi Ding, Zhangrui Qian, and Weiwei Sh
 an (Southeast University)\n---------------------\nBREW-RC: Bit-exact Recov
 ery of ECCs from Write Timing in ReRAM Crossbars\n\nWe present BREW-RC, a 
 non-invasive technique that uses a timing side channel to reverse engineer
  error-correcting codes (ECCs) in ReRAM crossbar memories. ECCs use a pari
 ty submatrix to extend data words with parity bits, forming codewords. The
 se parity bits cannot be read directly, but BREW-RC reve...\n\n\nTyler She
 aves (University of California, Santa Cruz); Alric Althoff (ARM); and Dust
 in Richmond (University of California, Santa Cruz)\n---------------------\
 nEmuDRop: A Minimalistic, Hardware-based Emulation Detection Approach thro
 ugh Intel Reserved Opcodes\n\nEmulation-based dynamic analysis detects mal
 icious software by observing runtime behavior in a controlled environment.
  \nMalware increasingly adopts evasion techniques to recognize such enviro
 nments and hide malicious activities. \nIn this paper, we propose EmuDRop,
  a minimalistic emulation-detection ...\n\n\nKaiyuan Rong (Tsinghua Univer
 sity); Ke Fang and Pengfei Qiu (Key Laboratory of System Software (Chinese
  Academy of Sciences) and State Key Laboratory of Computer Science, Instit
 ute of Software, Chinese Academy of Sciences); and Dapeng Ju and Dongsheng
  Wang (Tsinghua University & Zhongguancun Laboratory)\n-------------------
 --\nTime-Aware Active Calibration and Scheduling for N-Qubit Systems via B
 ayesian Optimization and Reinforcement Learning\n\nFrequent recalibration 
 of multi-qubit systems is essential to maintain hardware fidelity, but cal
 ibration itself is costly and subject to rapid parameter drift. This work 
 presents a novel framework for time-aware active calibration that combines
  Bayesian Optimization (BO) and Reinforcement Learning ...\n\n\nZiming Zha
 o and Tingting Li (Zhejiang University); Xiaofei Yue (Beijing Institute of
  Technology); Zhaoxuan Li (Institute of Computing Technology, CAS); and Ji
 anwei Yin (Zhejiang University)\n---------------------\nRTFL: Energy-Aware
  Federated Learning for AIoT Design Via Adaptive Quantization-based Multi-
 Agent Scheduling\n\nAlthough Federated Learning (FL) is becoming increasin
 gly popular in designing Artificial Intelligence of Things (AIoT) applicat
 ions, due to the varying computing and communication capabilities of resou
 rce-constrained devices, it suffers from the problems of slow convergence 
 and poor training perfor...\n\n\nJun Xia (University of Notre Dame) and Ju
 nqi Zhang, Zhaorong Zhu, Wenjie Chen, and Mingsong Chen (East China Normal
  University)\n---------------------\nHAP: Efficient Quantization Harnessin
 g Adaptive Precision for DNN Hardware Acceleration\n\nPost-training quanti
 zation (PTQ) avoids expensive training process and it is effective in acce
 lerating Deep Neural Networks (DNNs). Since the representation capacity of
  a quantizer decreases exponentially with precision, PTQ encounters fundam
 ental limitations in the low-precision domain. As an alter...\n\n\nErjing 
 Luo (University of Alberta), Xinkuang Geng and Honglan Jiang (Shanghai Jia
 o Tong University), leibo liu (Tsinghua University), and Jie Han (Universi
 ty of Alberta)\n---------------------\nLight-Bound Transformers: Hardware-
 Anchored Robustness for Silicon-Photonic Computer Vision Systems\n\nDeploy
 ing Vision Transformers (ViTs) on near-sensor analog accelerators demands 
 training pipelines that are explicitly aligned with device-level noise and
  energy constraints. We introduce a compact framework for silicon-photonic
  execution of ViTs that integrates \textbf{measured hardware noise}, \te..
 .\n\n\nXuming Chen (Case Western Reserve University), Deniz Najafi (New Je
 rsey Institute of Technology), Chengwei Zhou (Case Western Reserve Univers
 ity), Pietro Mercati (Intel), Arman Roohi (University of Illinois Chicago)
 , Mohsen Imani (University of California Irvine), Mahdi Nikdast (Colorado 
 State University), Shaahin Angizi (New Jersey Institute of Technology), an
 d Gourav Datta (Case Western Reserve University)\n---------------------\n3
 D-DuRA: Accelerating Next-Resolution Generation via 3D Near/In-Memory Arch
 itecture with Dual-Ring Sparse Attention\n\nVisual Autoregressive (VAR) mo
 del, via innovative next-resolution prediction, demonstrates significant p
 otential of GPT-style AR models in image generation. However, due to its c
 oarse-to-fine nature, the input token-map size grows dramatically with eac
 h step, resulting in excessive memory access and...\n\n\nZecheng Zhou, Yux
 iang Zhao, Xinyu Qu, Ruohang Xu, and Yufei Ma (Peking University)\n-------
 --------------\nSTAMP: Semiconductor Tool-chain Attestation through Wafer-
 Level Machine Learning-based Process Monitoring\n\nWe introduce a machine 
 learning approach for distinguishing between wafers fabricated using a san
 ctioned/ratified chain of tools on a semiconductor manufacturing floor and
  unsanctioned/unratified versions of the tool-chain based on metrology or 
 wafer acceptance test collected during manufacturing an...\n\n\nSuraag Sun
 il Tellakula (The University of Texas at Dallas); Ching-Yi Chang (Universi
 ty of Texas at Dallas); Matthew Nigh (University of California, San Diego)
 ; John Carulli (Advantest); and Yiorgos Makris (University of California, 
 San Diego)\n---------------------\nJanus: Compiler-Based Defense Against T
 ransient Execution Attacks Using ARM Hardware Primitives\n\nWe present Jan
 us, a compiler-based security framework that mit-\nigates transient execut
 ion attacks like Spectre and control-flow\nhijacking on ARM64 platforms. J
 anus integrates speculative execu-\ntion and control flow dependencies wit
 h PA modifiers, using PA and\nBTI microarchitectural features to pre...\n\
 n\nCiyan Ouyang, Peinan Li, Yubiao Huang, Dan Meng, and Rui Hou (Institute
  of Computing Technology, CAS)\n---------------------\nRISC-Q: A Generator
  for Real-Time Quantum Control System-on-Chips Compatible with RISC-V\n\nQ
 uantum computing imposes stringent requirements for the precise control of
  large-scale qubit systems, including, for example, microsecond-latency fe
 edback and nanosecond-precision timing of gigahertz signals – demands that
  far exceed the capabilities of conventional real-time systems. The rapidl
 y e...\n\n\nJunyi Liu, Yi Lee, Haowei Deng, Connor Clayton, Gengzhi Yang, 
 and Xiaodi Wu (University of Maryland, College Park)\n--------------------
 -\nSAEM: Stage-Aware Expert Management for Memory-Efficient MoE Inference 
 in Chain-of-Thought Reasoning\n\nChain-of-thought (CoT) prompting enhances
  LLM reasoning by decomposing tasks into intermediate steps, but it increa
 ses decoding latency and memory usage. Mixture-of-Experts (MoE) models imp
 rove scalability via sparse expert activation, yet expert weights often ex
 ceed GPU capacity. Existing runtimes ...\n\n\nYujie Zhang, Bin Gao, and Tu
 lika Mitra (National University of Singapore)\n\nTopics: Quantum\n\nTrack:
  DES6. Quantum Computing, Systems\n\nSession Chairs: Hokeun Kim (Arizona S
 tate University); BaekGyu Kim (Daegu Gyeongbuk Institute of Science and Te
 chnology); Xiang Chen (Peking University); Sangyeob Kim (Yonsei University
 ); Robert M. Radway (University of Pennsylvania); Prashanth Mohan (Univers
 ity of Pittsburgh); Xiaoxuan Yang (University of Virginia, Stanford Univer
 sity); Ramtin Zand (University of South Carolina); Hadi Kamali (University
  of Central Florida); Jiafeng Xie (Villanova University); Prabuddha Chakra
 borty (University of Maine); Junichiro Kadomoto (University of Tokyo); and
  Yosuke Ueno (RIKEN)
END:VEVENT
END:VCALENDAR