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BEGIN:VEVENT
DTSTAMP:20260730T152639Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T170600
DTEND;TZID=America/Los_Angeles:20260728T170600
UID:dac_DAC 2026_sess306_WIP502@linklings.com
SUMMARY:ML-Net: Enhanced Interconnect Modeling through Machine Learning–Ba
 sed Framework and Novel Double-π Networks
DESCRIPTION:Parsa Mirfasihi and Jatan Mandaliya (San Francisco State Unive
 rsity), Omar Yamak and Ahmed Shebaita (Synopsys), and Hamid Mahmoodi (San 
 Francisco State University)\n\nAccurate timing estimation in VLSI circuits
  is strongly influenced by interconnect parasitics. Current timing analysi
 s models the distributed RC network as either Lumped-Capacitance or π mode
 l. In this work, the Double-π model is introduced as a new RC representati
 on that captures higher-order distributed effects. Higher-order models off
 er more accuracy at the cost of increased computation cost. Using a single
  RC equivalent model for all interconnects often leads to either excessive
  computational cost or loss of accuracy. This work presents a machine lear
 ning–based framework that automatically and rapidly identifies the most su
 itable simplified RC representation—Lumped Capacitance, π, Double-π, or Di
 stributed—for precise gate delay estimation. The framework determines the 
 minimal RC model that maintains delay deviation within 1% of a fully distr
 ibuted network. A dataset of 10,000 randomized RC networks was generated f
 or each inverter size and timing arc to support model training and validat
 ion. Across all evaluated inverter sizes, the proposed framework achieved 
 an average classification accuracy—based on the best-performing model per 
 configuration—of 94% for T_p (propagation delay) and 93% for T_(rf-out)(ou
 tput transition time). The proposed framework enables dynamic and optimal 
 selection of interconnect models across a wide range of complexities and t
 ypes, including both mathematical and circuit-based representations, there
 by supporting accurate and scalable timing analysis for advanced VLSI desi
 gn flows.\n\nTrack: Student\n\n
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