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DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T175800
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UID:dac_DAC 2026_sess306_WIP3304@linklings.com
SUMMARY:Generalized Structural Bias Analysis for Corrupt-and-Correct Logic
  Locking
DESCRIPTION:Joseph Madera and Kyle Juretus (Villanova University)\n\nCorru
 pt-and-Correct (CAC) logic locking techniques offer strong resilience agai
 nst Boolean satisfiability (SAT) attacks. However, the additional perturba
 tion and correction circuitry can introduce detectable structural artifact
 s. Existing structural attacks and associated metrics remain narrowly scop
 ed, limiting their effectiveness for integrated circuit (IC) designers see
 king to assess structural bias. This paper formalizes a structural bias me
 tric that tracks the polarity of all internal circuit signals and quantifi
 es the deviation between circuit behavior under protected input patterns (
 PIPs) and behavior induced by random excitation. The metric can be evaluat
 ed with only a small number of tests, enabling a lightweight, design-time 
 diagnostic that identifies gates whose bias exceeds a threshold. This appr
 oach substantially improves the generality and practical utility of struct
 ural bias assessments compared to the state of the art. The developed metr
 ic is further employed to construct a structurally aware SAT attack (StrAT
 ) that directs the solver toward the most biased gates. Across the ISCAS'8
 5, MCNC, and ITC'99 combinational benchmarks locked with SFLL-HD0, SFLL-fl
 ex, and SFLL-rem, StrAT succeeds in 96.5% of the cases the original attack
  failed to find the key in the same time window.\n\nTrack: Student\n\n
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