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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T175700
DTEND;TZID=America/Los_Angeles:20260728T175800
UID:dac_DAC 2026_sess306_WIP3303@linklings.com
SUMMARY:Leak-CIM: A PVT-Robust and Energy-Efficient SRAM-CIM Macro Exploit
 ing Transistor Leakage
DESCRIPTION:Hiroto Tagata (Kyoto University), Hiromitsu Awano (Nagoya Univ
 ersity), and Takashi Sato (Kyoto University)\n\nWe propose Leak-CIM, a PVT
 -robust, low-power SRAM-based analog computing-in-memory macro for edge DN
 N inference. A voltage-mode MAC exploits subthreshold leakage of off-state
  transistors as ultra-high-resistance pseudo-resistors, suppressing dynami
 c shoot-through current and enabling rail-to-rail operation with wide dyna
 mic range. Post-fabrication N-well bias calibration compensates pMOS/nMOS 
 mismatch, improving MAC linearity in 22nm bulk CMOS, reducing NMSE from 6.
 82% to 0.53% at the worst corner. Leak-CIM achieves 1609 TOPS/W on CIFAR-1
 0 with a VGG-like binarized network at 87.52% accuracy.\n\nTrack: Student\
 n\n
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