BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T175700
DTEND;TZID=America/Los_Angeles:20260728T175700
UID:dac_DAC 2026_sess306_WIP3301@linklings.com
SUMMARY:Atto-Spinformer: An Energy-efficient Magneto Electric Spin Orbit L
 ogic-based Compute-in-Memory Transformer Architecture
DESCRIPTION:Hasita Veluri and Dilip Vasudevan (Lawrence Berkeley National 
 Laboratory)\n\nTransformers form the foundation of modern natural language
  processing, but their performance is limited by GPU memory bandwidth and 
 high energy consumption. In-memory computing (IMC) architectures mitigate 
 data transfer overhead, yet remain constrained by power-hungry interfaces.
  We present a novel ultra-low-power Magneto-Electric Spin Orbit (MESO)-bas
 ed IMC architecture optimized for dot product operation acceleration withi
 n transformers. By exploiting device non-volatility and a custom transmiss
 ion-gate-based pulse application scheme, our design eliminates DACs at the
  CMOS-MESO interface and reduce interface power by 20.3x. We propose a cus
 tom computation scheme that significantly lowers the floating-point operat
 ions required by IMC architectures to compute outputs. Combined with the l
 ow-power MESO devices, these techniques enable our accelerator to boost co
 mputational efficiency by 4.4x relative to conventional IMC designs and 2.
 6x relative to the NVIDIA A100 GPU.\n\nTrack: Student\n\n
END:VEVENT
END:VCALENDAR