BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T175600
DTEND;TZID=America/Los_Angeles:20260728T175700
UID:dac_DAC 2026_sess306_WIP3300@linklings.com
SUMMARY:A Fast and Accurate Surrogate Model for Clock-Mesh Timing Analysis
DESCRIPTION:Muhammad Hadir Khan and Matthew Guthaus (University of Califor
 nia, Santa Cruz)\n\nClock meshes are an essential technique in high-perfor
 mance VLSI systems to minimize skew and handle On-Chip Variation (OCV) esp
 ecially in nanometer technologies. However, analyzing meshes is difficult 
 due to reconvergent paths and multi-source drivers. The industrial standar
 d is to use SPICE simulations since static timing analysis (STA) tools can
  not handle mesh loops. SPICE simulations are accurate but slow, and appro
 ximate models miss critical effects like input slew and input skew. In thi
 s work, we propose a Graph Neural Network surrogate model of the clock mes
 h represented as a graph with augmented structural and physical features. 
 Trained on SPICE data, our model achieves high accuracy with average delay
  error of 1.70ps on unseen real designs versus 87.30ps from prior approxim
 ate models, while achieving speed-ups up to 3900x over multi-threaded SPIC
 E simulation enabling faster and accurate analysis for clock meshes. Furth
 ermore, we demonstrate the adaptability of our model through transfer lear
 ning and use it for OCV analysis.\n\nTrack: Student\n\n
END:VEVENT
END:VCALENDAR