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DTSTAMP:20260730T152640Z
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UID:dac_DAC 2026_sess306_WIP3298@linklings.com
SUMMARY:Trace and Chase: Empowering LLMs to Identify the Root Cause of Tes
 t Failures in RISC-V SoCs via Textualized Waveform
DESCRIPTION:Yicheng Zhong (Institute of Software, Chinese Academy of Scien
 ces; University of Chinese Academy of Sciences); Jingzheng Wu and Xiang Li
 ng (Institute of Software, Chinese Academy of Sciences); Hao Lyu (Institut
 e of Software, Chinese Academy of Sciences; University of Chinese Academy 
 of Sciences); and Zhiqing Rui, Tianyue Luo, and Chen Zhao (Institute of So
 ftware, Chinese Academy of Sciences)\n\nIdentifying the root causes of tes
 t failures in hardware designs constitutes a significant time bottleneck d
 uring the RISC-V SoC verification. Existing fault localization solutions s
 olely yield unverifiable locations without the causality between faults an
 d failures, and suffer from the impractical oracle requirements and unawar
 eness of dynamic behavior. We propose the LLM-based root cause analysis fr
 amework WaveAce targeting RISC-V SoCs. Leveraging texualized waveform, LLM
 s can perform substantiated reasoning over code and signals. Our evaluatio
 n across single-file defect benchmark and the OpenTitan SoC demonstrates t
 hat WaveAce outperforms or matches baseline in 79% cases and succeeds in l
 ocating five realistic bugs at scale.\n\nTrack: Student\n\n
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