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DTSTAMP:20260730T152640Z
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DTSTART;TZID=America/Los_Angeles:20260728T175600
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UID:dac_DAC 2026_sess306_WIP3296@linklings.com
SUMMARY:TIDE: A Triangular Interaction-Symmetric Dual-Systolic Engine for 
 Efficient Acceleration of Physics-Inspired Optimization
DESCRIPTION:Chia-Hua Yen (Department of Electronic Engineering, National T
 aipei University of Technology); Chin-Fu Nien (Dept. of Electronics and El
 ectrical Engineering, National Yang Ming Chiao Tung University); Ren-Guey 
 Lee (Department of Electronic Engineering, National Taipei University of T
 echnology); and Yuan-Ho Chen (National Taiwan University of Science and Te
 chnology)\n\nPhysics-inspired optimization (PIO) provides a unified framew
 ork for modeling structured interactions inspired by principles from stati
 stical physics, with applications spanning machine learning, operations re
 search, and VLSI design. Representative models—including Hopfield neural n
 etworks (HNNs), Boltzmann machines (BMs), and Ising machines (IMs)—encode 
 objectives as energy landscapes shaped by symmetric pairwise couplings. Ho
 wever, conventional hardware accelerators for these applications typically
  rely on dense matrix-multiplication datapaths that fail to exploit such s
 ymmetries, resulting in redundant multiply-accumulate (MAC) operations, ex
 cessive weight storage, and input staging delays. To address these ineffic
 iencies, we propose TIDE, a triangular interaction-symmetric dual-systolic
  engine that structurally exploits symmetry and sparsity in PIO workloads.
  TIDE stores only the upper-triangular portion of the coupling matrix and 
 performs a two-pass systolic traversal that aligns all data movements in b
 oth time and space, eliminating the input staging delays that conventional
  systolic arrays address using synchronization first-in-first-out (FIFO) b
 uffers. The architecture supports both binary and ternary input representa
 tions and incorporates an optional row-bypass path with compact 2-bit enco
 ding to reduce datapath complexity and storage overhead without modifying 
 the array structure. Compared to conventional weight-stationary (WS) and o
 utput-stationary (OS) architectures, TIDE achieves 33% lower latency and 5
 0% higher throughput than WS, and nearly 2× throughput over OS. At problem
  size N=2000, it reduces register storage by 60.0% vs. WS (8-bit), 62.6% v
 s. OS (8-bit), and 50.0% vs. DiP. With 2-bit encoding, TIDE further provid
 es a 4× storage reduction, yielding 90.0% savings vs. WS (8-bit), 90.7% vs
 . OS (8-bit), and 87.5% vs. DiP (8-bit).\n\nTrack: Student\n\n
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