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DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T175400
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UID:dac_DAC 2026_sess306_WIP3292@linklings.com
SUMMARY:High Fan-in Dynamic Leakage Suppression Standard Cells for Improve
 d Power, Performance, and Area in Ultra-low Power Circuits Authors:  Supri
 o Bhattacharya and Benton Highsmith Calhoun
DESCRIPTION:Suprio Bhattacharya and Benton Calhoun (University of Virginia
 )\n\nThis brief identifies a linear increase in the Elmore delay with fan-
 in size for Dynamic Leakage Suppression (DLS) logic structures, unlike qua
 dratic increase for Static CMOS logic. We leverage this property to design
  high fan-in (HFI) DLS standard cells (stdcells) that improves power, perf
 ormance, and area (PPA) of ultra-low power (ULP) chips for energy harvesti
 ng applications - an important domain not addressed by previous HFI works.
  We show important stdcell design considerations (timing, voltage swing) a
 nd PPA improvements using modeling and post-synthesis results on multiple 
 designs (including M0+/ RISCV based SoCs) which show over 53% power, 62% d
 elay, and 6% area reduction.\n\nTrack: Student\n\n
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