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DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T175400
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UID:dac_DAC 2026_sess306_WIP3291@linklings.com
SUMMARY:SPEEDY: Single-Step Reinforcement Learning Framework for Efficient
  Analog Circuit Sizing Optimization
DESCRIPTION:Chun-Yen Yao, Chun-Yen Wu, Matteo Guarrera, Alberto Sangiovann
 i-Vincentelli, Pierluigi Nuzzo, and Rikky Muller (University of California
 , Berkeley)\n\nReinforcement learning (RL) has shown to be promising in op
 timally solving the analog circuit sizing problem from simulations but oft
 en results in low sample efficiency and long execution times. We introduce
  SPEEDY, an actor-critic RL framework that leverages a single-step formula
 tion to improve sample efficiency. SPEEDY accelerates convergence by runni
 ng parallel, low-cost simulations that incrementally refine the design ran
 ge. Evaluated on two operational transconductance amplifier topologies and
  a state-of-the-art low-dropout regulator design, SPEEDY achieves up to 8x
  of improvement in convergence time, while improving the figure of merit w
 ith respect to comparable baseline methods.\n\nTrack: Student\n\n
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