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DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T175300
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UID:dac_DAC 2026_sess306_WIP3290@linklings.com
SUMMARY:SNN Accelerator Testing via Sparse Test Matrices
DESCRIPTION:Osita Ukwuaba and Cory Merkel (Rochester Institute of Technolo
 gy)\n\nSpiking neural network (SNN) accelerators offer the promise of ener
 gy efficiency and edge computing excellence when compared to traditional n
 eural networks. However, they are vulnerable to faults that can cause cata
 strophic failures in safety-critical applications. Manufacturing defects, 
 process variations, and malicious perturbations can alter SNN dynamics, le
 ading to significant performance degradation. To this end, we propose a re
 source-optimized testing methodology for SNNs using a normalized sparse ma
 trix, and the ensemble of Mean Absolute Membrane Potential Deviation (MAMP
 D) and Mean Absolute Spike Count Difference (MASCD) metrics. Our approach 
 is founded on the key insight that hardware faults induce measurable distr
 ibution shifts in neuronal activities, deviating faulty networks from thei
 r fault-free counterparts. Experimental validation shows that our sparse t
 est matrix approach, achieving up to 99.994% sparsity, attains 100% fault 
 coverage under bit flips, synaptic stuck-at, and neuron faults, while redu
 cing memory requirements by 43×, test generation time by 150K×, and comput
 ational cost by 55× compared to state-of-the-art methods.\n\nTrack: Studen
 t\n\n
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