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DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T175200
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UID:dac_DAC 2026_sess306_WIP3284@linklings.com
SUMMARY:Spec2Plan: A Robust LLM-Powered Framework for Verification Plan Ge
 neration and Evaluation
DESCRIPTION:Ting-Wei Chen, Tzu-Wei Tseng, Pei-Yun Yen, Xin-Hong Ou, Yun-Ru
  Li, Hong-Siang Wu, Jheng-Han Lai, and Yi-Xin Yang (National Taiwan Univer
 sity); Yi-Hang Chen, Gung-Yu Pan, and Ming-Hui Hsieh (Synopsys); and Chung
 -Yang (Ric) Huang (National Taiwan University)\n\nVerification planning is
  a critical but highly time and effort consuming stage in modern hardware 
 design flows, requiring engineers to interpret lengthy and complex specifi
 cations to derive comprehensive and high-quality verification plans. Moreo
 ver, manual plan authoring is an error-prone process that can lead to exte
 nded verification cycles and reducing productivity. We present Spec2Plan, 
 a structured LLM-driven framework for generating detailed, coverage-orient
 ed, and robust verification plans directly from hardware specifications. S
 pec2Plan combines four key components: (i) coverage-guided prompting, (ii)
  two-pass plan-and-generate strategy, (iii) testing techniques injection a
 nd (iv) iterative coverage refinement loop to generate robust verification
  plans. To assess plan quality, we developed a cross-LLM-validation framew
 ork that evaluates four key aspects: specification coverage, expert-plan a
 lignment, testing methodology robustness, and plan redundancy. Experiments
  on six OpenTitan IP blocks demonstrate that Spec2Plan significantly impro
 ves in all above metrics when compared to a one-pass prompting baseline. T
 hese results establish Spec2Plan as a practical step toward trustworthy an
 d automation-ready verification planning that can be seamlessly integrated
  into downstream verification workflows.\n\nTrack: Student\n\n
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