BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T175100
DTEND;TZID=America/Los_Angeles:20260728T175200
UID:dac_DAC 2026_sess306_WIP3283@linklings.com
SUMMARY:An Energy-Efficient Automated Hardware Generator for Edge BCI Syst
 ems
DESCRIPTION:Chih-Chyau Yang, Hao-Ruei Jiang, Chien-Ming Wu, and Chun-Ming 
 Huang (TSRI, NIAR)\n\nElectroencephalography (EEG) enables non-invasive mo
 nitoring of brain activity, but its high channel count and computationally
  intensive neural models pose major challenges to realizing energy-efficie
 nt edge accelerator hardware for real-time brain–computer interface (BCI) 
 systems. This work presents EEGDeep, an energy-efficient and fully automat
 ed hardware generator that bridges neural network model development and de
 ep-learning hardware accelerators for brain–computer interface (BCI) appli
 cations. The framework integrates three core modules: an EEG channel reduc
 tion module, which prunes non-informative channels to minimize model size 
 and computational load, enabling practical deployment in wearable applicat
 ions; an EEGDeep architecture evaluator, which performs constraint-aware n
 eural architecture and hardware exploration through model optimization, a 
 layer-reordering algorithm, and predefined deep-learning configurations to
  balance accuracy, area, latency, energy, and memory bandwidth; and an EEG
 Deep RTL generator, which converts optimized models into synthesizable RTL
  using a parameterized IP template. Using this automated framework, an EEG
 Deep design implemented in TSMC 90-nm CMOS technology achieves a 91.67% re
 duction in EEG channels, a processing latency of 1.43 ms per trial, and an
  energy consumption of 5.51 µJ per trial. These results correspond to a 65
 .9% reduction in area, a 98.49% improvement in latency, a 98.6% reduction 
 in energy consumption, and a 93.19% improvement in memory bandwidth compar
 ed with conventional implementations, demonstrating its potential for prac
 tical, low-energy, and real-time BCI applications.\n\nTrack: Student\n\n
END:VEVENT
END:VCALENDAR
