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DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T175100
DTEND;TZID=America/Los_Angeles:20260728T175100
UID:dac_DAC 2026_sess306_WIP3282@linklings.com
SUMMARY:Technology-oriented DTCO framework using neural compact modeling a
 nd polar level-set clustering
DESCRIPTION:Yongjeong Lee, Jeonghwan Kim, Jinyoung Lee, Youngbin Lee, Jeon
 gYeol Kim, and Jung Yun Choi (Samsung Electronics co. ltd)\n\nIn this pape
 r, we present a process-aware Design–Technology Co-Optimization (DTCO) fra
 mework that rapidly integrates transistor-level process shifts into circui
 t-level Power–Performance–Area (PPA) analysis. The approach combines Neura
 l Compact Models (NCM) with polar level-set clustering to identify and acc
 elerate process-dependent optima within the PPA trade-off space. A semi-su
 pervised NCM retargeting scheme reduces SPICE model development time by 98
 % while preserving model consistency and capturing median electrical shift
 s across diverse electrical targets, enabling the fast generation of techn
 ology-specific SPICE libraries and their corresponding PPA spaces. By mapp
 ing these libraries into a polar PPA domain, Pareto-based level-set cluste
 ring partitions technology behaviors into radial performance shells, layin
 g the foundation for a radial multi-objective optimization that effectivel
 y reduces the dimensionality of subsequent design-space exploration and si
 gnificantly increases the proportion of truly Pareto-optimal solutions wit
 hin the elite population. This unified NCM–polar-clustering framework deli
 vers interpretable, process-aware DTCO without TCAD or statistical samplin
 g, and can be directly calibrated with fab data for immediate industrial d
 eployment.\n\nTrack: Student\n\n
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