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DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T175000
DTEND;TZID=America/Los_Angeles:20260728T175100
UID:dac_DAC 2026_sess306_WIP3280@linklings.com
SUMMARY:Neuromorphic Ising Solver with Signed Spiking Neuron and Interleav
 ing Simulated Annealing for Large-scale Traveling Salesman Problem
DESCRIPTION:Seongsik Park (Korea Institute of Science and Technology) and 
 Jongkil Park (KIST)\n\nThe traveling salesman problem (TSP) is a fundament
 al combinatorial optimization problem with significant importance in vario
 us commercial and industrial domains. Numerous approaches have been propos
 ed to address the TSP, ranging from advanced algorithmic heuristics to spe
 cialized hardware architectures, but it remains challenging to implement, 
 especially for large-scale problems, due to the O(N^4) synaptic weight req
 uirement and device-level constraints. In this paper, we present a scalabl
 e digital neuromorphic Ising solver that integrates 8,192 signed spiking n
 eurons and an interleaving simulated annealing strategy on an AMD FPGA dev
 ice (XC7K160T). Virtual synaptic routing, implemented through address-even
 t-based communication, eliminates the need for fixed physical connectivity
 . The interleaving annealing reduces DRAM-access latency, achieving a 15% 
 reduction in per-iteration execution time, and reduces synaptic weight sto
 rage from O(N^4) to O(N) by storing only distance-dependent coupling terms
 . The single-core operation provides feasible solutions for TSPLIB instanc
 es with fewer than 32 cities, while the multi-core operation parallelizes 
 the solution of larger TSPs by partitioning the problem into hierarchical 
 subgraphs and merging the subgraph solutions using a constraint TSP(CTSP) 
 algorithm. With minimal per-core FPGA resource usage and a scalable archit
 ecture using virtual synaptic routing, the neuromorphic Ising solver can b
 e expanded to hundreds of neuromorphic Ising cores.\n\nTrack: Student\n\n
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