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DTSTART:19700308T020000
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DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T174900
DTEND;TZID=America/Los_Angeles:20260728T174900
UID:dac_DAC 2026_sess306_WIP3276@linklings.com
SUMMARY:Compact ML-based glitch propagation modeling of standard cells
DESCRIPTION:Anastasis Vagenas, Dimitrios Garyfallou, and George Stamoulis 
 (University of Thessaly)\n\nWith continuous technology scaling, accurate a
 nd efficient glitch modeling is critical for designing energy-efficient an
 d reliable ICs. In this work, we present a new gate-level approach for gli
 tch propagation modeling, utilizing Artificial Neural Networks (ANNs) to e
 stimate the key glitch shape characteristics, propagation delay, and power
  dissipation. Moreover, we introduce a framework that automates ANN genera
 tion and integrates them into standard cell libraries, exploring different
  architectures to balance accuracy and memory footprint. The proposed fram
 ework employs efficient techniques to generate realistic input glitch wave
 forms, reduce characterization effort, and improve model accuracy, memory 
 efficiency, and robustness. Experimental results on gates implemented in 7
  nm FinFET and 45 nm bulk CMOS technologies indicate that our models exhib
 it a strong correlation with SPICE, achieving a mean R2 score of 0.995 acr
 oss all gates and process, voltage, and temperature corners while maintain
 ing low memory demands. Furthermore, validation on paths extracted from re
 al circuits confirms our models' high accuracy and performance. Thus, our 
 approach could enable accurate full-chip glitch analysis and effectively g
 uide glitch reduction techniques.\n\nTrack: Student\n\n
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