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DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T174800
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UID:dac_DAC 2026_sess306_WIP3272@linklings.com
SUMMARY:ChipLite: High-level Performance Modeling Methodology for Automoti
 ve Chiplet Systems
DESCRIPTION:Diksha Moolchandani and Vinay Kumar (IMEC)\n\nAs automotive co
 mpute platforms evolve toward chiplet-based\narchitectures, the increasing
  heterogeneity introduces new challenges\nin exploring the architecture de
 sign space as a function of\nmetrics such as performance, power, area, and
  cost. In this pursuit,\ntraditional high-fidelity methodologies, using de
 tailed virtual\nprototypes, can be cumbersome to build and computationally
  prohibitive\nfor early-stage design exploration. In contrast, analytical\
 ntechniques such as roofline modeling offer rapid insights but depend\non 
 overly idealized assumptions — such as perfect computation–\ncommunication
  overlap, and sustained peak bandwidth —\nthat do not hold in heterogeneou
 s chiplet systems.\n\nTo address these limitations, we introduce ChipLite,
  a hybrid\nmodeling framework that extends the hierarchical roofline model
 \nwith workload-aware task mapping, realistic memory-access distributions,
 \nand inter-/intra-chiplet fabric flow modeling. Using\nChipLite, we analy
 ze three distinct chiplet architectures as example\ncase studies and demon
 strate how workload completion times\nare shaped by inter- and intra-chipl
 et congestion. Compared to\na naïve roofline model, for these case studies
 , ChipLite achieves\nup to 6x lower error in predicting execution time, wh
 ile retaining\norders-of-magnitude faster turnaround than detailed simulat
 ion\n\nTrack: Student\n\n
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