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DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T174800
DTEND;TZID=America/Los_Angeles:20260728T174800
UID:dac_DAC 2026_sess306_WIP3271@linklings.com
SUMMARY:Accelerating Functional Fault Grading for Flash and DRAM Designs
DESCRIPTION:Euisang Yoon, Arun Gogineni, and Saurabh Srivastava (Siemens);
  Eunjong Oh and Seongwook Lee (Samsung Electronics); Sungyun Yoo and Geonb
 eom Kwon (Siemens); and Yoseop Lee and Hyojin Choi (Samsung Electronics)\n
 \nFunctional fault grading is essential for post-silicon validation in sca
 n-limited designs, but simulation cost grows with fault and pattern volume
 . We propose an optimization-driven methodology combining static fault opt
 imization, fault clustering, design pruning, stimulus grading, dynamic fau
 lt optimization, and parallel fault simulation management. By leveraging b
 oth structural design information and stimulus behavior, the flow eliminat
 es redundant computation by performing optimized simulations tailored to f
 ault activation and propagation potential. Applied to a production-grade N
 AND Flash and DRAM designs, the approach achieved a 3.7x and 2x reduction 
 in simulation time, respectively, while preserving test coverage. The meth
 odology is broadly applicable to logic and SoC designs, offering scalable 
 fault grading without reliance on scan structures.\n\nTrack: Student\n\n
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