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DTSTAMP:20260730T152640Z
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DTSTART;TZID=America/Los_Angeles:20260728T173400
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UID:dac_DAC 2026_sess306_WIP3270@linklings.com
SUMMARY:LockRoute: A Spatial Locking Framework for Parallel Global Routing
DESCRIPTION:Amber Thrall (Washington State University), Vidya Chhabria (Ar
 izona State University), S. M. Ferdous and Mahantesh Halappanavar (Pacific
  Northwest National Laboratory), and Bala Krishnamoorthy (Washington State
  University)\n\nGlobal routing is a crucial step in VLSI design that has b
 ecome increasingly more complex as chip sizes and design scales grow. Many
  global routers divide the process into several stages: two-pin decomposit
 ion, congestion map generation, maze routing and layer assignment. Each of
  these stages requires routing thousands to millions of nets providing opp
 ortunities for parallelization. In this paper, we demonstrate that global 
 routing is not embarrassingly parallel and describe a lock-based approach 
 to shared-memory parallel global routing by identifying net dependencies t
 hrough the use of an R-tree. This lock framework is flexible enough to be 
 applied to every stage of the global routing pipeline. We evaluate our glo
 bal router on the ISPD 2008 and ISPD 2019 global routing contest benchmark
  suites. Our approach achieves a significant speedup in runtime without a 
 reduction in quality.\n\nTrack: Student\n\n
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