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DTSTAMP:20260730T152640Z
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DTSTART;TZID=America/Los_Angeles:20260728T172500
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UID:dac_DAC 2026_sess306_WIP3260@linklings.com
SUMMARY:Late Breaking Results: Analog Circuit Sizing via LLM-Guided Heuris
 tic Search with Metric Difficulty Awareness
DESCRIPTION:Xinyue Wu, Fan Hu, Jani Shaik, and Zixuan Li (Shanghai Jiao To
 ng University); Mohamed El-Hadedy (CalPoly Pomona); and Xinfei Guo (Shangh
 ai Jiao Tong University)\n\nAnalog sizing remains challenging since circui
 t parameters vary significantly across different Process Design Kits (PDKs
 ) and circuit topologies. While recent AI-based approaches attempt to auto
 mate this process, many rely on large models or struggle to generalize acr
 oss technology nodes. This paper propose EasySize, a lightweight LLM-assis
 ted sizing framework that leverages the difficulty of satisfying performan
 ce metrics within the search space to dynamically construct task-aware los
 s functions guiding heuristic search. EasySize generalizes to multiple ope
 rational amplifiers across 180nm–22nm nodes and achieves competitive perfo
 rmance while reducing simulation cost.\n\nTrack: Student\n\n
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